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In this paper, we propose a methodology for analyzing the near-field coupling between two surface mount device (SMD) inductors using a 3-dimensional electromagnetic (3D-EM) model. To develop the 3D-EM model, we first constitute the equivalent circuit of the SMD inductor from the measured impedance and derive the loss tangent using circuit parameters. Secondly, the loss tangent using damped harmonic oscillator model is introduced to extract the effective permeability of core magnetic material in the SMD inductor. The optimization algorithm is used to compare the two loss tangents. Then the effective permeability is used in the magnetic material for the 3D-EM modeling of the SMD inductor. The validity of the proposed 3D-EM model is confirmed by comparing the impedance and S-parameters obtained from both measured and EM-simulated values for the two near-field coupled SMD inductors. Finally, the near-field coupling effects between the two adjacent SMD inductors are visualized in terms of coupling path visualization (CPV) using the proposed 3D-EM model, which demonstrates its usefulness for near-field coupling analysis. [ABSTRACT FROM AUTHOR]

This study presents a comprehensive detailed analysis of the effect of five different random modulation switching schemes and their randomness levels on the elector magnetic interference (EMI) of designed simple and interleaved DC-DC buck converters for smartphone applications. The analyzed switching schemes are pulse width modulation (PWM), random pulse width modulation (RPWM), random pulse position modulation (RPPM), random carrier frequency modulation various duty (RCFMVD), and random carrier frequency modulation fixed duty (RCFMFD). The experimental analysis is performed for all aforementioned switching modulation schemes at the switching frequency of 20 kHz and different randomness levels (RL) (30% to 85%). For a fixed RL of 40%, the switching current harmonics/conducted emission (CE) levels are 5–10 dB/11 dBμV and 17 dB/14 dBμV lower for the RCFMVD case when compared to conventional PWM for both simple and interleaved buck-converters, respectively. The observed switching current harmonics and CE levels for interleaved schemes are around 23 dB and 12 dBμV lower when compared to the conventional simple buck converter scheme for the analyzed circuit configurations. The EMI levels decrease with the increase in the randomness levels from 30% to 85% with less variations in the output voltage level. The findings suggest that a interleaved buck converter circuit with the least-independent switching mechanisms and higher randomness is more appropriate for the reduction of both current spikes and CE levels with RCFMFD as the switching modulation scheme. [ABSTRACT FROM AUTHOR]

In this paper, a novel method to quantitatively analyze insulator degradation in a single layer solenoid is proposed. The suggested method employs renormalization of scattering parameters to efficiently detect changes of permittivity in a degraded solenoid. Firstly, a transmission line model, including a locally degraded part in the insulator, was developed, and it was determined that the phase information of the transmission parameter was very informative to check the permittivity change in the transmission line. To check the workability of this idea in a solenoid, a 30-turn single-layer solenoid was designed and fabricated, and 51 degraded states for mimicking insulation deterioration in each turn were introduced by installing additional insulator rings, which increased local relative permittivity. The phase data of the measured transmission parameter turned out to be useful for quantifying changes of the insulator in the solenoid. To maximize the detectability, the measured scattering parameters were renormalized with different reference impedances, which was very useful for detecting degradation in the transmission parameter. In this paper, detailed procedures for quantitatively analyzing degradation of an insulator are proposed and we verify that the suggested renormalization technique is very promising for effectively evaluating the degradation of a solenoid. [ABSTRACT FROM AUTHOR]

This study presents a near-field immunity test (NFIT) method for the fast debugging of radiated susceptibility of industrial devices. The proposed approach is based on the development of an NFIT setup which comprises of developed near-field electric and magnetic field probes and device under test (DUT). The developed small-size and handy near-field testing probes inject the high electric (up to 1000 V/m) and magnetic (up to 2.4 A/m) fields on the DUT in the radar pulse ranges (1.2 to 1.4 GHz and 2.7 to 3.1 GHz) with the lower fed input power (up to 15 W) from the power amplifier in the developed NFIT setup. The proof of concept is validated with the successful near-field immunity debugging of an electric power steering (EPS) device used in the automotive industry with the developed NFIT setup. The radiated susceptibility debugging test results of developed NFIT method and conventional method of ISO 11452-2 test setup turned out to be close to each other for the tested DUT in immunity performance. The proposed procedure has advantages of industry usefulness with fast, handy, and cost-effective radiated immunity debugging of the DUT without the requirement of large antenna, high-power amplifiers, optical DUT connecting harness, and an anechoic chamber as needed in ISO 11452-2 standard setup for the debugging analysis. [ABSTRACT FROM AUTHOR]

This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase. [ABSTRACT FROM AUTHOR]