Search

A systematic device-model calibration (extraction) methodology has been proposed to reduce parameter calibration time of advanced compact model for modern nano-scale semiconductor devices. The adaptive pattern search algorithm is a variant of the direct search method, which explore in the parameter space with adaptive searching step and direction. It is very straightforward, but powerful, in high dimensional optimization problem since adaptive step and direction are decided by simple computation. The proposed method iterates less but shows superior accuracy over the conventional method. It is possible to be applied to a behavioral or empirical model correspond to emerging devices, such as tunneling field-effect transistor (TFET) and negative capacitance field-effect transistor (NCFET) due to its universality in parameter calibration for the model accuracy. [ABSTRACT FROM AUTHOR]

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level. [ABSTRACT FROM AUTHOR]