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A comprehensive overview of PowderMEMS—a novel back-end-of-line-compatible microfabrication technology—is presented in this paper. The PowderMEMS process solidifies micron-sized particles via atomic layer deposition (ALD) to create three-dimensional microstructures on planar substrates from a wide variety of materials. The process offers numerous degrees of freedom for the design of functional MEMSs, such as a wide choice of different material properties and the precise definition of 3D volumes at the substrate level, with a defined degree of porosity. This work details the characteristics of PowderMEMS materials as well as the maturity of the fabrication technology, while highlighting prospects for future microdevices. Applications of PowderMEMS in the fields of magnetic, thermal, optical, fluidic, and electrochemical MEMSs are described, and future developments and challenges of the technology are discussed. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs. [ABSTRACT FROM AUTHOR]

High-performance and small-size on-chip inductors play a critical role in contemporary radio-frequency integrated circuits. This work presents a reliable surrogate modeling technique combining low-fidelity EM simulation models, response surface approximations based on kriging interpolation, and space mapping technology. The reported method is useful for the development of broadband and highly accurate data-driven models of integrated inductors within a practical timeframe, especially in terms of the computational expense of training data acquisition. Application of the constructed surrogate model for rapid design optimization of a compact on-chip inductor is demonstrated. The optimized EM-validated design solution can be reached at a low computational cost, which is a considerable improvement over existing approaches. In addition, this work provides a description and illustrates the usefulness of a multi-fidelity design optimization method incorporating EM computational models of graduated complexity and local polynomial approximations managed by an output space mapping optimization framework. As shown by the application example, the final design solution is obtained at the cost of a few high-fidelity EM simulations of a small-size integrated coil. A supplementary description of variable-fidelity EM computational models and a trade-off between model accuracy and its processing time complements the work. [ABSTRACT FROM AUTHOR]