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This review presents a concise overview of RF (radio frequency) power transistor behavior models, which is crucial for optimizing RF performance in high-frequency applications like wireless communication, radar, and satellites. The paper highlights the significance of accurate modeling in understanding transistor behavior and traces the evolution of behavior modeling techniques. Different behavior modeling strategies, such as LUT (look-up table) based models, polynomial equation-based models, and machine learning based models, are discussed along with their unique characteristics and modeling challenges. The review explores the difference between behavior models and the conventional empirical or physics-based modeling approaches, addressing the challenges of the accurate characterization of transistors at high frequencies and power levels. This paper concludes with an outlook of emerging trends, such as physical models combined with behavior models, shaping the future of RF power transistor modeling for more efficient communication systems.

A surface-potential-based analytical large-signal model, which is applicable to both ballistic and quasi-ballistic transport in InGaAs high electron mobility transistors, is developed. Based on the one-flux method and a new transmission coefficient, a new two-dimensional electron gas charge density is derived, while the dislocation scattering is novelly taken into account. Then, a unified expression for Ef valid in all the regions of gate voltages is determined, which is utilized to directly calculate the surface potential. The flux is used to derive the drain current model incorporating important physical effects. Moreover, the gate-source capacitance Cgs and gate-drain capacitance Cgd are obtained analytically. The model is extensively validated with the numerical simulations and measured data of the InGaAs HEMT device with the gate length of 100 nm. The model is in excellent agreement with the measurements under I-V, C-V, small-signal conditions, and large-signal conditions.

The egg production of laying hens is crucial to breeding enterprises in the laying hen breeding industry. However, there is currently no systematic or accurate method to identify low-egg-production-laying hens in commercial farms, and the majority of these hens are identified by breeders based on their experience. In order to address this issue, we propose a method that is widely applicable and highly precise. First, breeders themselves separate low-egg-production-laying hens and normal-laying hens. Then, under a halogen lamp, hyperspectral images of the two different types of hens are captured via hyperspectral imaging equipment. The vertex component analysis (VCA) algorithm is used to extract the cockscomb end member spectrum to obtain the cockscomb spectral feature curves of low-egg-production-laying hens and normal ones. Next, fast continuous wavelet transform (FCWT) is employed to analyze the data of the feature curves in order to obtain the two-dimensional spectral feature image dataset. Finally, referring to the two-dimensional spectral image dataset of the low-egg-production-laying hens and normal ones, we developed a deep learning model based on a convolutional neural network (CNN). When we tested the model's accuracy by using the prepared dataset, we found that it was 0.975 percent accurate. This outcome demonstrates our identification method, which combines hyperspectral imaging technology, an FCWT data analysis method, and a CNN deep learning model, and is highly effective and precise in laying-hen breeding plants. Furthermore, the attempt to use FCWT for the analysis and processing of hyperspectral data will have a significant impact on the research and application of hyperspectral technology in other fields due to its high efficiency and resolution characteristics for data signal analysis and processing.

The manipulation of biomedical particles, such as separating circulating tumor cells from blood, based on standing surface acoustic wave (SSAW) has been widely used due to its advantages of label-free approaches and good biocompatibility. However, most of the existing SSAW-based separation technologies are dedicated to isolate bioparticles in only two different sizes. It is still challenging to fractionate various particles in more than two different sizes with high efficiency and accuracy. In this work, to tackle the problems of low efficiency for multiple cell particle separation, integrated multi-stage SSAW devices with different wavelengths driven by modulated signals were designed and studied. A three-dimensional microfluidic device model was proposed and analyzed using the finite element method (FEM). In addition, the effect of the slanted angle, acoustic pressure, and the resonant frequency of the SAW device on the particle separation were systemically studied. From the theoretical results, the separation efficiency of three different size particles based on the multi-stage SSAW devices reached 99%, which was significantly improved compared with conventional single-stage SSAW devices.

The aim of this paper is to model the effects of threading dislocations on both gate and drain currents of AlGaN/GaN high electron mobility transistors (HEMTs). The fraction of filled traps increases with the threading dislocations, while the trapping effects cause a decrease in drain current and an increase in gate leakage current. To model the drain current drop, the two simplified RC subcircuits with diodes are proposed to capture the charge trapping/detrapping characteristics. The trap voltages V g_trap and V d_trap generated by RC networks are fed back into the model to capture the effects of traps on drain current. Considering acceptor-decorated dislocations, we present a novel Poole-Frenkel (PF) model to precisely describe the reverse leakage gate current, which plays a dominant role in the gate leakage current. The proposed model, which uses physical parameters only, is implemented in Verilog-A. It is in excellent agreement with the experimental data.

This paper investigates the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model. The skin and proximity effects, as well as the substrate loss effect, are considered and treated appropriately. The graphene resistance and inductance are combined into the circuit model. It is demonstrated that the electrical characteristics of the on-chip square spiral inductor can be improved by replacing copper with graphene. Moreover, graphene exhibits more effectiveness in improving the inductance in tapered inductors than uniform ones.

The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits' reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.

This paper presents an output offset minimized capacitance-to-digital interface for a MEMS accelerometer. With a gain-enhanced voltage-controlled oscillator (VCO)-based quantization loop, the interface is able to output a digital signal with improved dynamic range. For optimizing the output offset caused by nonideal factors (e.g., the bond-wire drift), a nested digital chopping feedback loop is embedded in the VCO-based quantization loop. It enables the interface to minimize the output offset without digital filtering and digital-to-analog conversion. The proposed architecture is well suited for dynamic range and offset improvements with low cost. Fabricated with a 0.18 μm Global Foundry (GF) CMOS process, the interface offers a 78 dB dynamic range with 0.4% nonlinearity from a single 2 V supply. With the input referred offset up to 1.3 pF, the offset cancellation loop keeps the DC output offset within 40 mV. The power dissipation is 6.5 mW with a bandwidth of 4 kHz.