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Field programmable gate arrays (FPGAs) have not only enhanced traditional sensing methods, such as pixel detection (CCD and CMOS), but also enabled the development of innovative approaches with significant potential for particle detection. This is particularly relevant in terahertz (THz) ray detection, where microbolometer-based focal plane arrays (FPAs) using microelectromechanical (MEMS) resonators are among the most promising solutions. Designing high-performance, high-pixel-density sensors is challenging without FPGAs, which are crucial for deterministic parallel processing, fast ADC/DAC control, and handling large data throughput. This paper presents a MEMS-resonator detector, fully managed via an FPGA, capable of controlling pixel excitation and tracking resonance-frequency shifts due to radiation using parallel digital lock-in amplifiers. The innovative FPGA architecture, based on a lock-in matrix, enhances the open-loop readout technique by a factor of 32. Measurements were performed on a frequency-multiplexed, 256-pixel sensor designed for imaging applications. [ABSTRACT FROM AUTHOR]

This paper presents a programmable digital filtering unit dedicated to operating with signals from infrared (IR) detection modules. The designed device is quite useful for increasing the signal-to-noise ratio due to the reduction in noise and interference from detector–amplifier circuits or external radiation sources. Moreover, the developed device is flexible due to the possibility of programming the desired filter types and their responses. In the circuit, an advanced field-programmable gate array FPGA chip was used to ensure an adequate number of resources that are necessary to implement an effective filtration process. The proposed circuity was assisted by a 32-bit microcontroller to perform controlling functions and could operate at frequency sampling of up to 40 MSa/s with 16-bit resolution. In addition, in our application, the sampling frequency decimation enabled obtaining relatively narrow passband characteristics also in the low frequency range. The filtered signal was available in real time at the digital-to-analog converter output. In the paper, we showed results of simulations and real measurements of filters implementation in the FPGA device. Moreover, we also presented a practical application of the proposed circuit in cooperation with an InAsSb mid-IR detector module, where its self-noise was effectively reduced. The presented device can be regarded as an attractive alternative to the lock-in technique, artificial intelligence algorithms, or wavelet transform in applications where their use is impossible or problematic. Comparing the presented device with the previous proposal, a higher signal-to-noise ratio improvement and wider bandwidth of operation were obtained. [ABSTRACT FROM AUTHOR]

This paper presents a highly efficient, low-power, compact mixed-signal sinusoidal current generator (CG) integrated circuit (IC) designed for bioelectrical impedance spectroscopy (BIS) with low total harmonic distortion (THD). The proposed system employs a 9-bit sine wave lookup table (LUT) which is simplified to a 4-bit data stream through a third-order digital delta–sigma modulator (ΔΣM). Unlike conventional analog low-pass filters (LPF), which statically limit bandwidth, the finite impulse response (FIR) filter attenuates high-frequency noise according to the operating frequency, allowing the frequency range of the sinusoidal signal to vary. Additionally, the output of the FIR filter is applied to a 6-bit capacitive digital-to-analog converter (CDAC) with data-weighted averaging (DWA), enabling dynamic capacitor matching and seamless interfacing. The sinusoidal CG IC, fabricated using a 65 nm CMOS process, produces a 5 μA amplitude and operates over a wide frequency range of 0.6 to 20 kHz. This highly synthesizable CG achieves a THD of 0.04%, consumes 19.2 μW of power, and occupies an area of 0.0798 mm2. These attributes make the CG IC highly suitable for compact, low-power bio-impedance applications. [ABSTRACT FROM AUTHOR]

With the increasing demand for accurate and robust positioning solutions, the use of GNSS antenna arrays has gained significant attention. However, their development and testing are frequently constrained by the inflexibility of traditional hardware platforms, often requiring extensive reconfiguration throughout the development cycle. This paper presents a platform based on a system on chip to develop a highly flexible software-controlled system that is capable of directly sampling up to 16 antenna elements. Multibeam digital beamforming is implemented using the available FPGA resources and the resulting signal is reproduced by the integrated DAC and can be connected to any conventional single antenna GNSS receiver. This paper presents the architecture of the platform, detailing its components and capabilities. Our experimental results demonstrate that the system can phase shift every channel with errors of less than 0.5° and can reconfigure 4 simultaneous beams of a 16-antenna array at speeds of 1.2 kHz, and 20 beams at around 400 Hz. The average delay introduced by each channel of the system is around 381 ns with a maximum deviation of 1.05 ns. The delay was also measured for the implementation using 4 beams, which achieves a slightly bigger average delay of 384.6 ns while keeping the variation to 5 to 6 ns. This system is intended to be used as the backbone for the development of antenna arrays and beamforming algorithms. Given its flexibility, it is not necessary to develop new hardware between development iterations or even for different systems, as only the software layer needs to be modified. Consequently, it is possible to expedite the development stage before producing dedicated solutions for industrial applications. [ABSTRACT FROM AUTHOR]

In this work, the system-level design of noise-shaping (NS) successive-approximation (SAR) analog-to-digital converters (ADCs) is investigated and analyzed. It is shown that despite the fact that the NS SAR architecture shares the same fundamental NS principle with the Σ Δ architecture, there are a few implementation differences that imply different considerations for optimum system-level design, particularly in the selection of the system oversampling ratio (OSR) and consequent resolution of the associated digital-to-analog converter (DAC) for a certain target overall resolution. In addition, the impacts of the OSR value on the power dissipation and figure-of-merit (FOM) are addressed in details. [ABSTRACT FROM AUTHOR]

This paper presents a thorough robust Class-AB power amplifier design and its application in pressure-mode sensor-on-chip nonlinearity correction. Considering its use in piezoresistive sensing applications, a gain-boosting-aided folded cascode structure is utilized to increase the amplifier's gain by a large amount as well as enhancing the power rejection ability, and a push–pull structure with miller compensation, a floating gate technique, and an adaptive output driving limiting structures are adopted to achieve high-efficiency current driving capability, high stability, and electronic environmental compatibility. This amplifier is applied in a real sensor nonlinearity correction on-chip system. With the help of a self-designed 7-bit + sign DAC and a self-designed two-stage operational amplifier, this system is compatible with nonlinear correction at different signal conditioning output values. It can also drive resistive sensors as small as 300 ohms and as high as tens of thousands of ohms. The designed two-stage operational amplifier utilizes the TSMC 0.18 um process, resulting in a final circuit power consumption of 0.183 mW. The amplifier exhibits a gain greater than 140 dB, a phase margin of 68°, and a unit gain bandwidth exceeding 199.76 kHz. The output voltage range spans from 0 to 4.6 V. The final simulation results indicate that the nonlinear correction system designed in this paper can correct piezoresistive sensors with a nonlinearity of up to ±2.5% under various PVT (Process–Voltage–Temperature) conditions. After calibration by this system, the maximum error in the output voltage is 4 mV, effectively reducing the nonlinearity to 4% of its original value in the worst-case scenario. [ABSTRACT FROM AUTHOR]

DC–DC buck converters have been designed by incorporating different control stages to drive the switches. Among the most commonly used controllers, the sliding mode control (SMC) and proportional-integral-derivative (PID) controller have shown advantages in accomplishing fast slew rate, reducing settling time and mitigating overshoot. The proposed work introduces the implementation of both SMC and PID controllers by using the field-programmable gate array (FPGA) device. The FPGA is chosen to exploit its main advantage for fast verification and prototyping of the controllers. In this manner, a DC–DC buck converter is emulated on an FPGA by applying an explicit multi-step numerical method. The SMC controller is synthesized into the FPGA by using a signum function, and the PID is synthesized by applying the difference quotient method to approximate the derivative action, and the second-order Adams–Bashforth method to approximate the integral action. The FPGA synthesis of the converter and controllers is performed by designing digital blocks using computer arithmetic of 32 and 64 bits, in fixed-point format. The experimental results are shown on an oscilloscope by using a digital-to-analog converter to observe the voltage regulation generated by the SMC and PID controllers on the DC–DC buck converter. [ABSTRACT FROM AUTHOR]

An automated device is designed to measure the density of a liquid material using hydrostatic pressure method. A low cost pressure sensor is calibrated and used to get highly accurate readings. The calibration is done by measuring the pressure values vs. the generated voltage signal. The calibration has been challenging due to the low accuracy of the sensor but proved to be highly effective in applications. The interface is developed using a microcontroller, motor drives, analog to digital converters and sensors. The device is designed to get several readings automatically by changing the positions of the device/liquid column heights to increase the accuracy. Also the device can be programmed to measure the real time density of a liquid continuously. The readings were analyzed and averaged by a software developed in python language. The instruments accuracy was tested against 3 liquid types, water, coconut oil, kerosene oil, and showed a low error (0.007%, 0.001%, and 0.002% respectively) compared to the readings of a standard Pycnometer. The low error percentages confirm the accuracy of the device and the effectiveness of the sensor calibrations. [ABSTRACT FROM AUTHOR]

A system-level implementation of a parallel-path hybrid switched-capacitor amplifier is presented in this paper. The proposed parallel-path amplifier incorporates a gain and slew rate-boosting switching path in parallel with an embedded assisted SAR path, aiming for IoT applications. As an alternative concept to the conventional analog topologies, the proposed amplifier combines nonlinear and linear paths to provide coarse and fine amplifications. In the coarse amplification, a high current is provided through a switching path for a fraction of time, which improves the slew rate and open-loop DC gain without adding significant static current. Moreover, high accuracy is achieved through the embedded assisted SAR path, which provides a resolution of 1/2N. In addition, each extra bit of the embedded SAR path improves the total open-loop DC gain by 6 dB. The theory of operation is performed to study how the switching and assisted SAR paths can enhance the amplifier's settling error. In addition, an existence trade-off between the coarse amplification error and the capacitive digital-to-analog converter's number of bits is investigated. The theory and system-level simulation show that the gain and slewing restrictions of the conventional topologies, especially in advanced CMOS technology, can be handled much easier by this parallel combination, where the switching path and assisted SAR path combination provides a high slewing capability and high DC open-loop gain. [ABSTRACT FROM AUTHOR]

The Lanzhou Heavy Ion Research Facility (LIRF) is the largest heavy ion research facility in China, providing a substantial volume of experimental data for fundamental research in nuclear physics. The Topmetal-CEE is a pixel readout chip specifically designed for tracking detectors. Within the Topmetal-CEE framework, the front-end amplifier and comparator necessitate precisely adjustable bias voltages. Hence, in this paper, a 14-bit resolution DAC with an R-2R resistor network structure is designed, along with an amplifier featuring high driving capabilities as the DAC driver, thus preventing potential impedance issues when driving large pixel arrays. Test results demonstrate that the DAC module, operating under a 3.3 V supply voltage, can consistently output voltages ranging from 0 to 1.8 V. Furthermore, the differential non-linearity error is less than 1.07 LSB, and the integral non-linearity error is less than 1.57 LSB. [ABSTRACT FROM AUTHOR]

This two-part work develops a comprehensive toolbox for the statistical characterization of nonlinear distortions of DAC-generated signal constellations to be transmitted over communication links, be they electronic (wireline, wireless) or photonic, Mach–Zehnder modulator (MZM)-based optical interconnects in particular. The all-analytic toolbox developed here delivers closed-form expressions for the second-order statistics (means, variances) of all relevant constellation metrics of the DACs' building blocks and of DAC-driven MZM-based optical transmitters, all the way to the slicer in the optical receivers over a linear channel with coherent detection. The key impairment targeted by the model is the random current mismatch of the ASIC devices implementing the DAC drivers. In particular the (skew-)centrosymmetry of the DAC metrics is formally derived and explored. A key applicative insight is that the conventional INL/DNL (Integral NonLinearity/Differential NonLinearity) constellation metrics, widely adopted in the electronic devices and circuits community, are not quite useful in the context of communication systems, since these metrics are ill-suited to predict communication link statistical performance. To rectify this deficiency of existing electronic DAC metrics, we introduce modified variants of the INL|DNL, namely the integral error vector (IEV) and the differential error vector (DEV) constellation metrics. The new IEV|DEV represent straightforward predictors of relevant communication-minded metrics: error vector magnitude (EVM) treated here in Part I, and Symbol/Bit Error-Rates (SER, BER) treated in the upcoming Part II of this paper. [ABSTRACT FROM AUTHOR]

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications. [ABSTRACT FROM AUTHOR]

This paper presents an analog delay-locked loop (DLL) with a digital coarse lock and error compensation, designed to enhance locking speed in duty-cycled operation while ensuring reliability. To accelerate coarse locking speed and prevent coarse lock failure, the proposed DLL combines a low-resolution digital-to-analog converter (DAC) with an analog method for accurate lock range identification, efficiently handling scenarios where the DAC's limited resolution could lead to failure. Additionally, it enables the rapid control of voltage adjustments by disconnecting a loop filter during the coarse lock, eliminating the need for a buffer. The DLL improves the coarse lock process reliability by compensating for potential false lock errors caused by circuit non-idealities, such as residual RC delay and amplifier offset. Furthermore, it reuses the previously identified DAC input for the duty-cycled operation to significantly reduce relock time. To mitigate the risk of potential false lock resulting from changes in locking conditions, it can update the previous DAC input upon relocking, ensuring more reliable relocking. The proposed DLL, implemented in a 28 nm CMOS process, reduces initial lock and relock times by an average of 49.3% and 65.9% at a supply voltage of 0.5 V, and 42.4% and 70.2% at 1 V, respectively, compared to the conventional analog DLL. [ABSTRACT FROM AUTHOR]

Each application of neurostimulators requires unique stimulation parameter specifications to achieve effective stimulation. Balancing the current magnitude with stimulation resolution, waveform, size, and channel count is challenging, leading to a loss of generalizability across broad neural interfaces. To address this, this paper proposes a highly scalable, programmable neurostimulator with a System-on-Chip (SOC) capable of 32 channels of independent stimulation. The compliance voltage reaches up to ±22.5 V. A pair of 8-bit current-mode DACs support independent waveforms for source and sink operations and feature a user-selectable dual range for low-current intraparenchymal microstimulation with a resolution of 4.31 μ A/bit, as well as high current stimulation for spinal cord and DBS applications with a resolution of 48.00 μ A/bit, achieving a wide stimulation range of 12.24 mA while maintaining high-resolution biological stimulation. A dedicated communication protocol enables full programmable control of stimulation waveforms, effectively improving the range of stimulation parameters. In vivo electrophysiological experiments successfully validate the functionality of the proposed stimulator. This flexible stimulator architecture aims to enhance its generality across a wide range of neural interfaces and will provide more diverse and refined stimulation strategies. [ABSTRACT FROM AUTHOR]

Photonic integrated circuits (PIC) devices are impacted by fabrication tolerances and therefore, prior knowledge of such variations could improve the PIC fabrication process and overall yield. This paper presents a method for predicting the fabrication impacts on a telecommunication optical digital to analog converter (oDAC)-based pulse amplitude modulator level four (PAM-4) transmitter as a case study where the certainty of this passive device is subjected to random variation. Our findings allow us to estimate the production yield in a fabrication scenario using the symbol error rate (SER) benchmark and this contributes to the study of the viability of oDAC PAM-4 transmitters to replace conventional electrical digital to analog converter (eDAC) PAM-4 transmitters. [ABSTRACT FROM AUTHOR]

This research explores the forefront of all-optical data processing systems through the utilization of carrier reservoir semiconductor optical amplifiers (CR-SOAs). Recent advancements have showcased the successful design and implementation of CR-SOA-based combinational systems, incorporating pivotal elements like half adders, half subtractors, digital-to-analog converters, latches, header recognition, and header processors. These breakthroughs signify a significant stride towards the realization of faster and more efficient optical logic systems. This study delves into the distinctive characteristics of CR-SOA-based Mach–Zehnder interferometer (MZI) functioning as an XOR gate, emphasizing their transformative potential in information processing. By integrating them into the architecture of an all-optical 4-bit parity generator and checker, the research underscores the practicality of CR-SOA technology in all-optical processing, offering unprecedented speeds and facilitating enhanced data processing capabilities at a remarkable speed of 120 Gb/s return-to-zero pulses. In evaluating the performance of the proposed scheme, the research employs the quality factor metric. This assessment not only yields quantitative insights into the efficacy of CR-SOA-based logic systems but also establishes a critical benchmark for their practical implementation. The study further explores the impact of key data signals and CR-SOA parameters on this metric. The outcomes demonstrate the ability of the CR-SOA-based MZI to cascade and form more intricate logic circuits, thereby highlighting the versatility and potential of this innovative approach in advancing the landscape of all-optical data processing. [ABSTRACT FROM AUTHOR]

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital). [ABSTRACT FROM AUTHOR]

The feasibility of implementing digital predistortion for next-generation wireless communication is faced with a dilemma due to the ever-increasing demand for faster data rates. This causes the utilized bandwidth to increase significantly, as seen in the 5G NR standard in which bandwidths as high as 400 MHz are utilized. Hence, the development of new predistortion techniques in which the forward and feedback paths operate at lower sampling rates is of utmost importance to realize efficient and practical predistortion solutions. In this work, a novel predistortion technique is presented by which the predistortion is divided between the digital and analog domains. The predistorter is composed of a memoryless AM/AM gain function that is implementable in the analog domain, and a nonlinear model with memory effects in the digital domain to relax the sampling rate requirements on both the forward and feedback paths. Experimental validation was carried out with a 20 MHz and a 40 MHz 5G signal, and the results indicate minimal linearization degradation with a sampling rate reduction of 50% and 30%, respectively. This sampling rate reduction is concurrently applied in the digital-to-analog converter of the forward path and the analog-to-digital converter of the feedback path. [ABSTRACT FROM AUTHOR]

A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology. [ABSTRACT FROM AUTHOR]

Long coherence times at room temperature make the NV center a promising candidate for quantum sensors and quantum computers. The necessary coherent control of the electron spin triplet in the ground state requires microwave π pulses in the nanosecond range, obtained from the Rabi oscillation of the mS spin states of the magnetic resonances of the NV centers. Laboratory equipment has a high temporal resolution for these measurements but is expensive and, therefore, uninteresting for fields such as education. In this work, we present measurement electronics for NV centers that are optimized for microcontrollers. It is shown that the Rabi frequency is linear to the output of the digital-to-analog converter (DAC) and is used to adapt the time length π of the electron spin flip, to the limited pulse width resolution of the microcontroller. This was achieved by breaking down the most relevant functions of conventional laboratory devices and replacing them with commercially available integrated components. The result is a cost-effective handheld setup for coherent control applications of NV centers. [ABSTRACT FROM AUTHOR]

This brief presents a comprehensive analysis of the output-dependent modulation (ODM) in a current-steering digital-to-analog converter (CS-DAC) based on the differential-quad switching (DQS) structure. A mathematical model is proposed to accurately describe ODM, which is categorized into two types: output transition errors and boundary effect errors. A novel approach of adding isolation devices is introduced and reinterpreted to mitigate the effect of ODM. The simulation results indicate that the inclusion of isolation devices efficiently suppresses the odd harmonics at mid-to-high frequency by a value that is 13 dB lower than before. Experimental validation is conducted on a 16-bit 250 MS/s CS-DAC fabricated in a 180 nm process. [ABSTRACT FROM AUTHOR]

In this article, we address the problem of synchronizing multiple analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chains in a multi-channel system, which is constrained by the sampling frequency and inconsistencies among the components during system integration. To evaluate and compensate for the synchronization differences, we propose a pulse compression shape-based algorithm to measure the entire delay parameter of the ADC/DAC chain, which achieves sub-sampling resolution by mapping the shape of the discrete pulse compression peak to the signal propagation delay. Moreover, owing to the matched filtering in the pulse compression process, the algorithm exhibits good noise performance and is suitable for wireless scenarios. Experiments verified that the algorithm can achieve precise measurements with sub-sampling resolution in scenarios where the signal-to-noise ratio (SNR) is greater than −10 dB. [ABSTRACT FROM AUTHOR]

In this paper, a temperature measurement system with NTC (Negative Temperature Coefficient) thermistors was designed. An MCU (Micro Control Unit) primarily operates by converting the voltage value collected by an ADC (Analog-to-Digital Converter) into the resistance value. The temperature value is then calculated, and a DAC (Digital-to-Analog Converter) outputs a current of 4 to 20 mA that is linearly related to the temperature value. The nonlinear characteristics of NTC thermistors pose a challenging problem. The nonlinear characteristics of NTC thermistors were to a great extent solved by using a resistance ratio model. The high precision of the NTC thermistor is obtained by fitting it with the Hoge equation. The results of actual measurements suggest that each module works properly, and the temperature measurement accuracy of 0.067 °C in the range from −40 °C to 120 °C has been achieved. The uncertainty of the output current is analyzed and calculated with the uncertainty of 0.0014 mA. This type of system has broad potential applications in industry fields such as the petrochemical industry. [ABSTRACT FROM AUTHOR]

Quantum Key Distribution (QKD) has garnered significant attention due to its unconditional security based on the fundamental principles of quantum mechanics. While QKD has been demonstrated by various groups and commercial QKD products are available, the development of a fully chip-based QKD system, aimed at reducing costs, size, and power consumption, remains a significant technological challenge. Most researchers focus on the optical aspects, leaving the integration of the electronic components largely unexplored. In this paper, we present the design of a fully integrated electrical control chip for QKD applications. The chip, fabricated using 28 nm CMOS technology, comprises five main modules: an ARM processor for digital signal processing, delay cells for timing synchronization, ADC for sampling analog signals from monitors, OPAMP for signal amplification, and DAC for generating the required voltage for phase or intensity modulators. According to the simulations, the minimum delay is 11ps, the open-loop gain of the operational amplifier is 86.2 dB, the sampling rate of the ADC reaches 50 MHz, and the DAC achieves a high rate of 100 MHz. To the best of our knowledge, this marks the first design and evaluation of a fully integrated driver chip for QKD, holding the potential to significantly enhance QKD system performance. Thus, we believe our work could inspire future investigations toward the development of more efficient and reliable QKD systems. [ABSTRACT FROM AUTHOR]

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper focuses on the digital closed-loop design for a step-up converter with hybrid switching. For this purpose, for the first time, the control-to-output small-signal transfer function of a hybrid switching converter is determined in the rational form. Based on it, a type 3 analog controller is designed, and then, its digitized counterpart is found, and the digital controller is designed using a digital signal processor. The closed-loop operation is then validated both through simulation and practical implementation. [ABSTRACT FROM AUTHOR]

This paper introduces an innovative differential sampling technique for calibrating AC waveforms, leveraging a commercially available 16-bit digital-to-analog converter (DAC) as the reference standard. The novelty of this approach lies in its enhanced stability over traditional direct sampling methods, especially as the frequency of the AC waveform increases. Notably, this technique provides a cost-effective sampler alternative to the differential sampling methods that rely on a programmable Josephson voltage standard (PJVS). A critical aspect of this methodology is the precise measurement of the DAC's output voltage, for which a static measurement strategy is adopted to utilize the exceptional linearity and transfer accuracy of the Keysight 3458A (Santa Rosa, CA, USA) in its standard DCV mode. The differential sampling method has demonstrated good accuracy, achieving a near 1 µV/V agreement with a pulse-driven AC Josephson voltage standard (ACJVS) across a 40 Hz to 200 Hz frequency range. The method attained an expanded uncertainty (k = 2) of 1 part in 106 while measuring a 0.707107 VRMS sine wave at 50 Hz, showcasing its efficacy in precise AC waveform calibration. [ABSTRACT FROM AUTHOR]

In this paper, a wireless potentiostat code-named ElectroSense, for interfacing of wearable electrochemical biosensors, will be presented. The system is devoted to non-invasive monitoring of glucose in wearable medical applications. Differently from other potentiostats in literature, which use digital-to-analog converters (DACs) as discrete components or integrated in high-end microcontrollers, in this work the pulse width modulation (PWM) technique is exploited through PWM-DAC approach to generate signals. The ubiquitous presence of integrated PWM peripherals in low-end microcontrollers, which generally also integrate analog-to-digital converters (ADCs), enables both the generation and acquisition of read-out signals on a single cheap electronic device without additional hardware. By this way, system's production costs, power consumption, and system's size are greatly reduced with respect to other solutions. All these features allow the system's adoption in wearable healthcare Internet-of-things (IoT) ecosystems. A description of both the sensing technology and the circuit will be discussed in detail, emphasizing advantages and drawbacks of the PWM-DAC approach. Experimental measurements will prove the efficacy of the proposed electronic system for non-invasive monitoring of glucose in wearable medical applications. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter–amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta–sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively. [ABSTRACT FROM AUTHOR]

Recently, the incidence of, and interest in, respiratory diseases has been amplified by severe acute respiratory syndrome coronavirus (SARS-CoV-2) and other respiratory diseases with a high prevalence. Most of these diseases require mechanical ventilation for homecare and clinical therapy. Herein, we propose a portable and non-invasive mechanical fan (NIV) for home and clinical applications. The NIV's core is a turbine for airflow generation, which can provide and monitor a positive two-level pressure of up to approximately 500 lpm at 50 cmH2O according to the inspiration/expiration phase. After calibration, the proposed NIV can precisely set the airflow with a pressure between 4 cmH2O and 20 cmH2O, providing a versatile device that can be used for continuous positive airway pressure (CPAP) or bilevel positive airway pressure (BiPAP). The airflow is generated by a turbine monitored using a mass flow sensor. The whole NIV is monitored with a 16 MHz clock microcontroller. An analog-to-digital converter is used as the input for analog signals, while a digital-to-analog converter is used to drive the turbine. I2C protocol signals are used to manage the display. Moreover, a Wi-Fi system is interfaced for the transmission/reception of clinical and technical information via a smartphone, achieving a remote-controlled NIV. [ABSTRACT FROM AUTHOR]

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as C n = 2 × C n − 1 , the variable capacitor C n of ADC1 can be updated to be closest to the sum of C n − 1 of ADC1 and C n − 1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the C n of ADC1 can be connected with two of the C n − 1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update C n . This process is iterated, until C n is in agreement with the sum of two of C n − 1 . Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively. [ABSTRACT FROM AUTHOR]

This paper investigates a real-time process generator of wideband signals, which calculates waveforms in a field-programmable gate array (FPGA) using the high-level synthesis (HLS) method. To obtain high-resolution and wide-swath images, the generator must produce multiple modes of large time-bandwidth product (TBP) linear frequency modulation (LFM) signals. However, the conventional storage method is unrealistic as it requires huge storage resources to save pre-computed waveforms. Therefore, this paper proposes a novel processing approach that calculates waveforms in real-time based simply on parameters such as the sampling frequency, bandwidth, and time width. Additionally, this paper implements predistortion through the polynomial curve to approximate phase errors of the system. The parallelizing process in the FPGA is necessary to satisfy the high-speed requirement of a digital-to-analog converter (DAC); however, repeatedly multiplexing real-time calculation consumes extensive logic and DSP resources, potentially exceeding FPGA limitations. To address this, this paper proposes a piecewise linear algorithm to conserve resources, which processes the polynomial only once, acquires the difference in two adjacent values through the register and pipeline, and then adds this increment to facilitate parallel computations. The performance of this proposed generator is validated through simulation and implemented in experiments with an X-band airborne SAR system. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable hybrid Analog to Digital Converter (ADC) designed specifically for bio-signal processing, aiming to achieve low power consumption and high area efficiency. The proposed ADC utilizes a combination of 10-bit Most Significant Bit (MSB) Successive Approximation Register (SAR) and 2–4-bit Least Significant Bit (LSB) Single Slope (SS) architectures. The SS architecture incorporates the Dummy Capacitor Quantization Method (DCQM) which employs a 10-bit MSB dummy capacitor. This dummy capacitor can be configured to represent the 2-LSBs or reconstruct 4-LSBs. The reconfigurability of the ADC is achieved through the control of the reset timing of a 5-bit counter enabled by an external signal. The proposed ADC was fabricated using a Complementary Metal Oxide Semiconductor (CMOS) n-well 1-poly 8-metal process. Experimental measurements revealed that the ADC operates at a speed of 454 kS/s with power consumption of 18.7 μW. The Effective Number of Bits (ENoB) achieved by the ADC is 10.9 bits based on a 14-bit scale or 10.2 bits based on a 12-bit scale. The Figure of Merit (FoM) for the ADC is calculated to be 21.5 fJ/step for the 14-bit scale and 22.1 fJ/step for the 12-bit scale. [ABSTRACT FROM AUTHOR]

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process. [ABSTRACT FROM AUTHOR]

Successive approximation register (SAR) analog-to-digital converters (ADC) have the advantages of a simple structure, low power consumption and a small area compared with other types of ADCs, and thus, high-performance SAR ADCs have always been a hot research topic in the industry. In this paper, a 12-bit SAR ADC design with calibration using a hybrid RC digital-to-analog converter(RC DAC) structure is proposed to improve the conversion accuracy of the ADC and reduce the circuit area at the same time. The analog supply voltage and reference voltage of the ADC are 3.3 V, and the digital supply voltage is 1.2 V. The ADC adopts a mixed digital–analog design scheme, in which the internal comparator, latch, DAC capacitor array, etc., are analog parts, and the rest of the SAR algorithms and calibration algorithms are all implemented in digital Verilog code, with a conversion accuracy of 0.8 mV and a calibration accuracy of 0.5 LSB. The ADC can be selectively calibrated, and the simulation shows that the accuracy of the calibrated ADC can be guaranteed to be within 2 LSB under a 14 MHz digital clock with a sampling rate of 1 MHz. After simulation at a sampling rate of 1 MHz and an input frequency of 244 Hz sine wave, the effective bit count of the ADC is 9.54 bits and the SFDR is 63.71 dB. The circuit consumes 1.78 mW with a 3.3 V supply voltage. The overall layout core area is 411 μ m × 517 μ m. [ABSTRACT FROM AUTHOR]

This work introduces a novel architecture for implementing a parallel coherent photonic digital-to-analog converter (PDAC), designed to transform parallel digital electrical signals into corresponding analog optical output, convertible to analog electrical signals using photodiodes. The proposed architecture incorporates microring resonator-based modulators (MRMs), phase shifters, and symmetric multimode interference couplers. Efficient modulation is achieved by MRMs utilizing carrier depletion-induced refractive index changes, while metal heaters facilitate tuning of the ring resonator resonance wavelength. The proposed architecture is scalable to higher bit resolutions and exhibits a dynamic range limited by MRM's sensitivity to applied bias and noise levels. Experimental results of the fabricated chip in the silicon-on-insulator (SOI) platform showcase the successful realization of a 4 GSample/sec conversion rate in a 2-bit resolution operation, along with a stationary conversion of four parallel DC digital signals into 16 analog intensity levels in a 4-bit PDAC configuration. The study encompasses a proof-of-concept experimental demonstration of 8 Gbps data conversion, along with a 50 Gbps data conversion rate using the optimized design in the simulation, affirming the accuracy and quality of the PDAC architecture. These findings contribute to the advancement of PDAC technology, providing insights into performance characteristics, limitations, and potential applications. [ABSTRACT FROM AUTHOR]

This paper aims to outline the process of dimensioning a controller tailored for a fourth-order step-down converter. In order to conduct a thorough small-signal analysis, it is imperative to find the state–space model in matrices form. Given its fourth-order nature, the control-to-output transfer function also aligns with this order, although its degree is ultimately reduced to a second-order using the tfest function. It is remarkable that the design of the type III error amplifier assumes a central position in the overall controller design process. The theoretical analysis was then subjected to rigorous validation via simulation, with particular attention paid to the step response in both input voltage and output resistance. This study developed from the desire to validate the efficacy of reducing the control-to-output transfer function degree using the tfest function, aiming to highlight a fourth-order converter to which controller design theory can be applied, related to that for a second-order converter. [ABSTRACT FROM AUTHOR]

This paper presents a significant contribution to high-fidelity audio technology through the comprehensive design and implementation of an advanced audio-grade preamplifier integrated with a high-performance digital-to-analog converter (DAC). The versatility of the digital section allows seamless integration of audio sources from Universal Serial Bus (USB), Bluetooth, or Sony-Philips Digital interface (SPDIF). In addition, the preamplifier accommodates various analog sources, offering flexibility to users. The unique architecture features an innovative resistor network-based DAC and precision components in the analog section, paving the way for achieving unparalleled audio fidelity. The measured distortion values are remarkably low, with a total harmonic distortion plus noise (THD+N) of only 0.03%. Furthermore, the system exhibits a signal-to-noise ratio (SNR) of 87 dB, comparable to industry benchmark. The hardware design sections went into meticulous details, providing an in-depth exploration of each block of the project. The inclusion of test and measurement data from the actual prototype enhances the credibility of the proposed work. This research not only showcases the theoretical operation of the preamplifier and DAC stage but also validates the practical implementation through many rounds of testing and validation. Our proposed work contributes to the field of high-fidelity audio by presenting a novel solution that is comparable to industry standards. The design's adaptability to many different audio sources, coupled with robust performance metrics, positions it as a benchmark in the field of audio reproduction. The measurement results and findings presented in this paper are poised to influence future advancements in HiFi audio technology. [ABSTRACT FROM AUTHOR]

In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter's result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm2 and consumes an average power of 540.6 μW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts. [ABSTRACT FROM AUTHOR]

Currently, cloud storage servers are controlled by a third-party administrator. This semi-trusted approach gives rise to security concerns. Therefore, in cloud computing, some protocols use a key manager to encrypt the user's private data before uploading the data to the cloud. However, the security concerns that arise from the use of a key manager are not yet solved. In this respect, in this paper, a provably secure user cloud data access control protocol (DAC) is proposed based on existing cloud storage. Empirical tests confirm that the proposed approach is highly secure against adaptive selective ciphertext attacks and has excellent resistance to message attacks. A comprehensive performance evaluation, including time measurements, is conducted and the protocol is compared to other protocols, revealing the efficient file upload and download processes of the proposed approach. The results demonstrate the protocol's strong security, practicality, and operational efficiency. [ABSTRACT FROM AUTHOR]

Humankind has entered a new era wherein a main characteristic is the convergence of various technologies providing services and exerting a major impact upon all aspects of human activity, be it social interactions with the natural environment. Fixed networks are about to play a major role in this convergence, since they form, along with mobile networks, the backbone that provides access to a broad gamut of services, accessible from any point of the globe. It is for this reason that we introduce a forward-looking approach for fixed networks, particularly focused on Fixed 6th Generation (F6G) networks. First, we adopt a novel classification scheme for the main F6G services, comprising six categories. This classification is based on the key service requirements, namely latency, capacity, and connectivity. F6G networks differ from those of previous generations (F1G–F5G) in that they concurrently support multiple key requirements. We then propose concrete steps towards transforming the main elements of fixed networks, such as optical transceivers, optical switches, etc., such that they satisfy the new F6G service requirements. Our study categorizes the main networking paradigm of optical switching into two categories, namely ultra-fast and ultra-high capacity switching, tailored to different service categories. With regard to the transceiver physical layer, we propose (a) the use of all-optical processing to mitigate performance barriers of analog-to-digital and digital-to-analog converters (ADC/DAC) and (b) the exploitation of optical multi-band transmission, space division-multiplexing, and the adoption of more efficient modulation formats. [ABSTRACT FROM AUTHOR]

Featured Application: The proposed technique can be applied to minimize capacitor mismatch error in pipeline analog-to-digital converters. This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. Although the calibration method is employed in a 1.5-bit stage architecture, which uses a gain-of-two switched-capacitor amplifier, it is applicable to different bit-per-stage architectures. The ADC linearity significantly improves after calibration, and this is verified through simulations and measurements. [ABSTRACT FROM AUTHOR]

Computing-in-Memory (CIM) is a novel computing architecture that enormously improves energy efficiency and reduces computing latency by avoiding frequent data movement between the computation and memory units. Currently, digital CIM is regarded as more suitable for high-precision operations represented in floating-point arithmetic, as it is not limited by the bit width of ADC/DAC in analog CIM. However, the development of DCIM still faces two problems: On the one hand, mainstream SRAM-based DCIM memory cells introduce large area overheads, which contain at least six transistors per cell. On the other hand, existing DCIM solutions can only support the computing precision up to FP32, failing to meet the demands of high-accuracy application scenarios. To overcome these problems, this work designs a novel SOT-MRAM-based digital CIM macro (MDCIM) with higher area/energy efficiency and achieves double-precision floating-point (FP64) computation with a modified fused multiply–accumulate (FMA) module. The proposed design is synthesized with a 55 nm CMOS technology node, achieving 0.62 mW power consumption, 26.9 GOPS/W, and 0.332 GOPS/mm2 energy efficiency at 150 MHz with 1.08 V supply. Circuit level simulation results show that the MDCIM can achieve higher area utilization compared to previous SRAM-based CIM designs. [ABSTRACT FROM AUTHOR]

This paper presents a new control method for a bidirectional DC–DC LLC resonant topology converter. The proposed converter can be applied to power the conversion between an energy storage system and a DC bus in a DC microgrid or bidirectional power flow conversion between vehicle-to-grid (V2G) behavior and grid-to-vehicle (G2V) behavior. Furthermore, such a converter can be applied to energy storage systems for decentralized renewable energy generation systems, such as solar and wind power. In addition, this converter can be combined with a bidirectional inverter to allow energy storage in the system to improve the safety, stability, and power quality of the microgrid. In the proposed circuit structure, we use a bidirectional DC–DC LLC, which has the advantages of a higher voltage conversion ratio, lower part count, simpler control than similar converters such as DAB, CLLC, and L–LLC converters, and bidirectional power flow and electrical isolation. Specifically, to extend the battery life, it can be employed as a control strategy for discharging the energy stored in the battery (SOC) and reducing the temperature rise generated by the internal solid electrolyte interphase (SEI) when discharging the battery under the variation in distributed energy resource (DER) generation and load demand. To realize the bidirectional power conversion without using any auxiliary inductor and only changing the control strategy, the forward step-down power conversion was based on pulse frequency modulation (PFM) control, and the reverse step-up power conversion was based on pulse width modulation (PWM) control. In this paper, we introduce the bidirectional converter topology and its control strategy for the DC microgrid battery energy storage system. Finally, a 500 W prototype is built to verify the effectiveness of the proposed converter. [ABSTRACT FROM AUTHOR]

With the explosive growth of micro-video applications, the transmission burden of fronthaul and backhaul links is increasing, and meanwhile, a lot of energy consumption is also generated. For reducing energy consumption and transmission delay burden, we propose a cell-free massive multiple-input multiple-output (CF-mMIMO) system in which the cache on the access point (AP) is used to reduce the load on the link. In this paper, a total energy efficiency (EE) model of a cache-assisted CF-mMIMO system is established. When optimizing EE, forming the co-operation cluster is critical. Therefore, we propose an energy-efficient joint design of content caching, AP clustering, and low-resolution digital-to-analog converter (DAC) in a cache-assisted CF-mMIMO network based on deep reinforcement learning. This scheme can effectively cache content in APs and select the appropriate DAC resolution. Then, taking into account the channel state information and user equipment (UE)'s content request preference, a deep deterministic policy gradient algorithm is used to jointly optimize the cache strategy, AP clustering, and DAC resolution decisions. Simulation results show that the energy efficiency of the proposed scheme is 4% higher than that of other schemes without the resolution optimization and is much higher than that of the only AP clustering without the joint design of content caching and channel quality. [ABSTRACT FROM AUTHOR]

A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based MDLLs, the lock time increases as the value of the multiplication factor N decreases. However, the proposed variable-gain TDC can minimize the MDLL lock time by adjusting the TDC gain according to the change in N value. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL clock multiplier generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. It achieves a fast lock time of only 3 × M (=9) reference clock cycles when N/M = 10/3 at 2.0 GHz and demonstrates a simulated peak-to-peak jitter of 3.16 ps at 3.2 GHz when N/M = 16/3. Additionally, it occupies an active area of only 0.02 mm2 (=200 μm × 100 μm) and consumes a power of 2.3 mW at 1.0 GHz. [ABSTRACT FROM AUTHOR]

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works. [ABSTRACT FROM AUTHOR]

This paper proposes a solar-powered isolated DC–DC converter for high-power applications. The main aim of this paper is to achieve voltage regulation in the output side of the converter and to integrate a lossless active clamp flyback circuit (LACF) to compensate for the high-voltage issues that arise from one-stage DC–DC converters. Hardware is developed with a power rating of 2 kW to test the performance of the proposed circuit. The circuit is designed using low-voltage devices and features such as soft switching and regeneration due to the LACF, which enhances efficiency. A novel luminous control algorithm is presented to improve the converter performance. The proposed circuit's performance and feasibility are compared with existing converter parameters, such as the number of components in the circuit, voltage rating, and regeneration. [ABSTRACT FROM AUTHOR]

A piezoelectric vibration sensing system (PVSS) was devised in this study and employed for the purpose of vibration sensing in machining. The system comprises three primary components, wherein the sensor is utilized for the collection and conversion of energy, subsequently transmitting it to the data acquisition card (DAC) via a low-noise cable. The crux of the entire system lies in the upper computer-based control application, which facilitates the transmission of instructions to the DAC for data acquisition and transmission. The integration of Wi-Fi data transfer capability between the DAC and the computer serves to eliminate the principal issue associated with employing the sensor as a voltage source. The sensitivity of the designed device was calibrated utilizing commercial accelerometers, while an aluminum workpiece was fabricated to conduct vibration and machining tests in order to verify the performance of the PVSS. The shaker excitation experiment yielded a peak voltage of 0.05 mV, thereby substantiating that the PVSS can more accurately discern the natural frequency of the workpiece below 5000 Hz compared to commercial accelerometers. The experiments verify that the devised PVSS can precisely measure vibrations during the milling process, and can be implemented for the purpose of detecting machining stability. [ABSTRACT FROM AUTHOR]

As the preferred architecture for high-speed and high-resolution analog-to-digital converters (ADC), the accuracy of pipelined ADC is limited mainly by various errors arising from multiple digital-to-analog converters (MDAC). This paper presents a multi-dimensional (M-D) MDAC calibration based on a genetic algorithm (GA) in a 12-bit 750 MS/s pipelined ADC. The proposed M-D MDAC compensation model enables capacitor mismatch and static interstage gain error (IGE) compensation on the chip and prepares for subsequent background calibration based on a pseudo-random number (PN) injection to achieve accurate compensation for dynamic IGE. An M-D coefficient extraction scheme based on GA is also proposed to extract the required compensation coefficients of the foreground calibration, which avoids falling into local traps through MATLAB. The above calibration scheme has been verified in a prototype 12-bit 750 MS/s pipelined ADC. The measurement results show that the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are increased from 49.9 dB/66.7 dB to 59.6 dB/77.5 dB with the proposed calibration at 25 °C. With the help of background calibration at 85 °C, the SNDR and SFDR are improved by 3.4 dB and 8.8 dB, respectively. [ABSTRACT FROM AUTHOR]