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This paper proposes a further generalization of the fractional-order filters whose limiting form is that of the second-order filter. This new filter class can also be regarded as a superset of the recently reported power-law filters. An optimal approach incorporating constraints that restricts the real part of the roots of the numerator and denominator polynomials of the proposed rational approximant to negative values is formulated. Consequently, stable inverse filter characteristics can also be achieved using the suggested method. Accuracy of the proposed low-pass, high-pass, band-pass, and band-stop filters for various combinations of design parameters is evaluated using the absolute relative magnitude/phase error metrics. Current feedback operational amplifier-based circuit simulations validate the efficacy of the four types of designed filters and their inverse functions. Experimental results for the frequency and time-domain performances of the proposed fractional-order band-pass filter and its inverse counterpart are also presented.

In this paper a concept for the efficient design of a series of floating fractional-order elements (FOEs) is proposed. Using even single or a very limited number of so-called “seed” FOEs it is possible to obtain a wide set of new FOEs featuring fractional order α being in the range [−n,n], where n is an arbitrary integer number, and hence enables to overcome the lack of commercial unavailability of FOEs. The systematic design stems from the utilization of a general immittance converter (GIC), whereas the concept is further developed by proposing a general circuit structure of the GIC that employs operational transconductance amplifiers (OTAs) as active elements. To show the efficiency of the presented approach, the use of only up to two “seed” FOEs with a properly selected fractional order αseed as passive elements results in the design of a series of 51 FOEs with different α being in the range [−2,2] that may find their utilization in sensor applications and the design of analog signal processing blocks. Comprehensive analysis of the proposed GIC is given, whereas the effect of parasitic properties of the assumed active elements is determined and the optimization process described to improve the overall performance of the GIC. Using OTAs designed in 0.18 μμm TSMC CMOS technology, Cadence Virtuoso post-layout simulation results of the GIC are presented that prove its operability, performance optimization, and robustness of the proposed design concept.