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A compact probe for charged particle imaging, with potential applications in source activity mapping and radio-guided surgery was designed and tested. The development of this technology holds significant implications for medical imaging, offering healthcare professionals accurate and efficient tools for diagnoses and treatments. To fulfill the portability requirements of these applications, the probe was designed for battery operation and wireless communication with a PC. The core sensor is a dual-layer CMOS SPAD detector, fabricated using 150 nm technology, which uses overlapping cells to produce a coincidence signal and reduce the dark count rate (DCR). The sensor is managed and interfaced with a microcontroller, and custom firmware was developed to facilitate communication with the sensor. The performance of the probe was evaluated by characterizing the on-board SPAD detector in terms of the DCR, and the results were consistent with the characterization measurements taken on the same chip samples using a purposely developed benchtop setup. [ABSTRACT FROM AUTHOR]

Silicon radiation detectors, a special type of microelectronic sensor which plays a crucial role in many applications, are reviewed in this paper, focusing on fabrication aspects. After addressing the basic concepts and the main requirements, the evolution of detector technologies is discussed, which has been mainly driven by the ever-increasing demands for frontier scientific experiments. [ABSTRACT FROM AUTHOR]

Small-pitch 3D pixel sensors have been developed to equip the innermost layers of the ATLAS and CMS tracker upgrades at the High Luminosity LHC. They feature 50 × 50 and 25 × 100 μ m 2 geometries and are fabricated on p-type Si–Si Direct Wafer Bonded substrates of 150 μ m active thickness with a single-sided process. Due to the short inter-electrode distance, charge trapping effects are strongly mitigated, making these sensors extremely radiation hard. Results from beam test measurements of 3D pixel modules irradiated at large fluences ( 10 16 n e q / cm 2 ) indeed demonstrated high efficiency at maximum bias voltages of the order of 150 V. However, the downscaled sensor structure also lends itself to high electric fields as the bias voltage is increased, meaning that premature electrical breakdown due to impact ionization is a concern. In this study, TCAD simulations incorporating advanced surface and bulk damage models are used to investigate the leakage current and breakdown behavior of these sensors. Simulations are compared with measured characteristics of 3D diodes irradiated with neutrons at fluences up to 1.5 × 10 16 n e q / cm 2 . The dependence of the breakdown voltage on geometrical parameters (e.g., the n + column radius and the gap between the n + column tip and the highly doped p + + handle wafer) is also discussed for optimization purposes. [ABSTRACT FROM AUTHOR]

A monolithic pixel sensor with high spatial granularity (35 × 40 μm2) is presented, aiming at thermal neutron detection and imaging. The device is made using the CMOS SOIPIX technology, with Deep Reactive-Ion Etching post-processing on the backside to obtain high aspect-ratio cavities that will be filled with neutron converters. This is the first monolithic 3D sensor ever reported. Owing to the microstructured backside, a neutron detection efficiency up to 30% can be achieved with a 10B converter, as estimated by the Geant4 simulations. Each pixel includes circuitry that allows a large dynamic range and energy discrimination and charge-sharing information between neighboring pixels, with a power dissipation of 10 µW per pixel at 1.8 V power supply. The initial results from the experimental characterization of a first test-chip prototype (array of 25 × 25 pixels) in the laboratory are also reported, dealing with functional tests using alpha particles with energy compatible with the reaction products of neutrons with the converter materials, which validate the device design. [ABSTRACT FROM AUTHOR]

Fully Depleted Monolithic Active Pixel Sensors (FD-MAPS) represent an appealing alternative to hybrid detectors for radiation imaging applications. We have recently demonstrated the feasibility of FD-MAPS based on a commercial 110 nm CMOS technology, adapted using high-resistivity substrates and backside post-processing. A p/n junction diode, fabricated on the detector backside using low-temperature processing steps after the completion of the front-side Back End of Line (BEOL), is reverse-biased to achieve the full depletion of the substrate and thus fast charge collection by drift. Test diodes including termination structures with different numbers of floating guard rings and different pitches were fabricated together with other Process Control Monitor structures. In this paper, we present the design of the backside diodes, together with results from the electrical characterization of the test devices, aiming to improve understanding of the strengths and limitations of the proposed approach. Characterization results obtained on several wafers demonstrate the effectiveness of the termination rings in increasing the breakdown voltage of the backside diodes and in coping with the variability of the passivation layer characteristics. A breakdown voltage exceeding 400 V in the worst case was demonstrated in devices with 30 guard rings with 6 μm pitch, thus enabling the full depletion of high-resistivity substrates with a thickness larger than or equal to 300 μm. Additionally, we show the first direct comparison for this technology of measured pixel characteristics with 3D TCAD simulations, proving a good agreement in the extracted operating voltages. [ABSTRACT FROM AUTHOR]

The paper presents the simulation studies of 10 μ m pitch microstrips on a fully depleted monolithic active CMOS technology and describes their potential to provide a new and cost-effective solution for particle tracking and timing applications. The Fully Depleted Monolithic Active Microstrip Sensors (FD-MAMS) described in this work, which are developed within the framework of the ARCADIA project, are compliant with commercial CMOS fabrication processes. A set of Technology Computer-Aided Design (TCAD) parametric simulations was performed in the perspective of an upcoming engineering production run with the aim of designing FD-MAMS, studying their electrical characteristics, and optimizing the sensor layout for enhanced performance in terms of low capacitance, fast charge collection, and low-power operation. A fine pitch of 10 μ m was chosen to provide high spatial resolution. This small pitch still allows readout electronics to be monolithically integrated in the inter-strip regions, enabling the segmentation of long strips and the implementation of distributed readout architectures. The effects of surface radiation damage expected for total ionizing doses of the order of 10 to 10 5 krad were also modeled in the simulations. The results of the simulations exhibit promising performance in terms of timing and low power consumption and motivate R&D efforts to further develop FD-MAMS; the results will be experimentally verified through measurements on the test structures that will be available from mid-2021. [ABSTRACT FROM AUTHOR]