Search

This paper introduces an indoor-monitoring LiDAR sensor for patients with Alzheimer disease residing in long-term care facilities (LTCFs), and this sensor exploits an optoelectronic analog front-end (AFE) to detect light signals from targets by utilizing on-chip avalanche photodiodes (APDs) realized in a 180 nm CMOS process and a neural processing unit (NPU) used for motion detection and decisions, especially for incidents of falls occurring in LTCFs. The AFE consists of an on-chip CMOS P+/N-well APD, a linear-mode transimpedance amplifier, a post-amplifier, and a time-to-digital converter, whereas the NPU exploits network sparsity and approximate processing elements for low-power operation. This work provides a potential solution of low-cost, low-power, indoor-monitoring LiDAR sensors for patients with Alzheimer disease in LTCFs. [ABSTRACT FROM AUTHOR]

This paper describes the implementation of an antenna-in-package (AiP) with a dual polarization function, supporting a three-dimensional (3D) beamforming operation. In order to implement 3D beamforming, a Yagi-type end-fire antenna supporting each of the x and y directions and a patch-type broadsided antenna supporting the z-direction were implemented. The broadside antennas have dual polarization functions so that they can be received in any direction. Each antenna was implemented in four array structures to support beamforming operations. The broadside antenna was designed in a 2 × 2 array structure, with a patch-type antenna and two linear dual polarization functions. The single antenna operated with a gain of 6 dBi, an E-plane beam width of ±45 degrees, and an H-plane beam width of ±50 degrees and had an antenna gain of 9~11 dBi as well as a vertical/horizontal forming operation with a radiation angle of ±22 degrees The end-fire antenna unit was designed in a 1 × 4 array structure with a Yagi-type antenna. The single antenna had a gain of 4 dBi, with an antenna gain of 8 dBi in the array structure, and it was improved to 11 dBi by adding a parasitic array director. The final end-fire antenna unit had a radiation angle of ±11 degrees and a beamforming coverage of ±45 degrees The vertical and horizontal design results were secured for reception in any direction, and all the array antennas had a return loss of 10 dB or less in the entire frequency band, from 57 to 66 GHz. [ABSTRACT FROM AUTHOR]

Inaccurate computing is found to be a high-speed, low-power and energy-efficient alternative to accurate computing for error-tolerant applications. In this context, this paper analyzes the usefulness of inaccurate computing for a digital image processing application, viz. digital image blending, which has been less explored. We analyze the use of inaccurate addition for image blending used in applications such as photo editing and computer graphics. For experimentation, we considered blending two digital images using accurate and inaccurate addition separately. We considered many inaccurate addition architectures which are suitable for implementation in both FPGA and ASIC design environments to perform a comparative analysis. We found that an inaccurate addition with an optimum inaccuracy produces a similar quality of blended image as obtained using accurate addition. The quality of blended images is quantified using standard metrics such as the peak signal-to-noise ratio and the structural similarity index measure. In particular, an inaccurate adder, M-HERLOA, was found to be preferable for image blending from the combined perspectives of quality of blended image, error metrics and design metrics. We implemented the accurate and inaccurate adders corresponding to an optimum inaccuracy in FPGA and ASIC design environments. We considered a Xilinx Artix-7 FPGA for an FPGA-based implementation and a 32/28 nm CMOS standard digital cell library for an ASIC type standard cell-based implementation. The results show that, for an FPGA-based implementation, M-HERLOA enables a reduction in delay by 13%, requires 50% fewer LUTs and 49% fewer registers and consumes 24.3% less on-chip power compared to the accurate high-speed FPGA adder while yielding a blended image of good quality. For an ASIC type standard cell-based implementation, M-HERLOA enables a reduction in delay by 64.6% (24.4%), requires 43% (82.4%), less area and dissipates 63% (67.8%) less power than the accurate carry ripple adder (carry look-ahead adder). [ABSTRACT FROM AUTHOR]

This paper reports a novel, one-dimensional dense array of asymmetrical metal-oxide-semiconductor field-effect-transistor (MOSFET) THz detector, which has been fabricated in GlobalFoundries 55-nm CMOS technology. Compared with other technologies, the Si-based complementary metal-oxide-semiconductor (CMOS) dominates in industrial applications, owing to its easier integration and lower cost. However, as the frequency increases, the return loss between the antenna and detector will increase. The proposed THz detector has a short-period grating structure formed by MOSFET fingers in the array, which can serve as an effective antenna to couple incident THz radiation into the FET channels. It not only solved the problem of return loss effectively, but also greatly reduced the detector area. Meanwhile, since the THz signal is rectified at both the source and drain electrodes to generate two current signals with equal amplitude but opposite directions, the source drain voltage is not provided to reduce the power consumption. This leads to a poor performance of the THz detector. Therefore, by using an asymmetric structure for the gate fingers position to replace the source drain voltage, the performance of the detector in the case of zero power consumption can be effectively improved. Compared with the symmetrical MOSFET THz detector, Rv is increased by 183.3% and NEP is decreased by 67.7%. [ABSTRACT FROM AUTHOR]

Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and product bits. We considered many 8-bit digital images for blending and the blended images obtained using exact and inexact multipliers are shown, which demonstrates the usefulness of inexact multiplication for image blending. For 8 × 8 image blending, one of our inexact array multipliers viz. IAM01-VC8 was found to achieve 63.3% reduction in area, 21% reduction in critical path delay, 72.3% reduction in power dissipation, and 78.1% reduction in energy compared to the exact array multiplier. In addition, IAM01-VC8 achieved 60.6% reduction in area, 9.7% reduction in critical path delay, 64.7% reduction in power dissipation, and 68.1% reduction in energy compared to the high-speed exact 8 × 8 multiplier that was automatically synthesized using a logic synthesis tool. The exact and inexact multipliers were physically realized using 32/28 nm CMOS process technology. [ABSTRACT FROM AUTHOR]

In this paper, we describe DECAL, a prototype Monolithic Active Pixel Sensor (MAPS) device designed to demonstrate the feasibility of both digital calorimetry and reconfigurability in ASICs for particle physics. The goal of this architecture is to help reduce the development and manufacturing costs of detectors for future colliders by developing a chip that can operate both as a digital silicon calorimeter and a tracking chip. The prototype sensor consists of a matrix of 64 × 64 55 μ m pixels, and provides a readout at 40 MHz of the number of particles which have struck the matrix in the preceding 25 ns. It can be configured to report this as a total sum across the sensor (equivalent to the pad of an analogue calorimeter) or the sum per column (equivalent to a traditional strip detector). The design and operation of the sensor are described, and the results of chip characterisation are reported and compared to simulations. [ABSTRACT FROM AUTHOR]

The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices. [ABSTRACT FROM AUTHOR]

This paper presents the design and simulation of a mass sensitive Lamb wave microsensor with CMOS technology provided by SilTerra. In this work, the effects of the metalization ratio variation on the transmission gain, total harmonic distortion (THD), and two different resonant modes (around 66 MHz and 86 MHz) are shown. It has been found that the metalization ratio can be adjusted in order to obtain a compromise between transmission gain and sensitivity, depending on the design criteria. By adding a Si 3 N 4 layer on top of the device, a five-fold improvement in transmission gain is reached. It was also shown that the transmission of the input differential IDT configuration is 20% more efficient than a single terminal. With this combination, the mass sensitivity is about 114 [cm 2 /gr]. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34   m m 2 . Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology's nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current. [ABSTRACT FROM AUTHOR]

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison. [ABSTRACT FROM AUTHOR]

To investigate the relationship between the specifications degradation of a low-noise amplifier (LNA) and temperature, we experimentally investigated the degradation characteristics of the specifications of the LNA at different temperatures. The small-signal gain (S21) of the LNA decreases with increasing temperature. This paper discusses and analyzes the experimental results in detail, and the reasons for the degradation of LNA specifications with temperature changes are known. Finally, we have tried to use the structure already available in the literature for the PA temperature compensation circuit for the temperature compensation of the LNA. The results show that the existing circuit structure for PA temperature compensation in the literature can also effectively compensate for the S21 and NF degradation of the LNA due to the temperature increase. [ABSTRACT FROM AUTHOR]

In this paper, a wide-band noise-canceling (NC) current conveyor (CC)-based CMOS low-noise amplifier (LNA) is presented. The circuit employs a CC-based approach to obtain wide-band input matching without the need for bulky inductances, allowing broadband performance with a very small area used. The NC technique is applied by subtracting the input transistor's noise contribution to the output and achieves a noise figure (NF) reduction from 4.8 dB to 3.2 dB. The NC LNA is implemented in a UMC 65-nm CMOS process and occupies an area of only 160 × 80 μm2. It achieves a stable frequency response from 0 to 6.2 GHz, a maximum gain of 15.3 dB, an input return loss (S11) < −10 dB, and a remarkable IIP3 of 7.6 dBm, while consuming 18.6 mW from a ±1.2 V DC supply. Comparisons with similar works prove the effectiveness of this new implementation, showing that the circuit obtains a noteworthy performance trade-off. [ABSTRACT FROM AUTHOR]

This paper presents a differential 19.6–39.4 GHz broadband low-noise amplifier (LNA) in 65-nm CMOS technology. The LNA consists of two cascode stage and one common-source stage. To achieve a wide bandwidth and low average noise figure, inter-stage peak-gain distribution technique and transformer-based triple-coupled technique are developed. Besides, a new compact T-coil-based network is proposed to neutralize the parasitic capacitors and enlarge the gain. The measure results show that the 3-dB bandwidth is from 19.6 to 39.4 GHz, the maximum gain is 23.5 dB, and the noise figure (NF) is from 3.7 to 5.8 dB. The dc power comsumption is 46 mW with 1V supply voltage. The input P1dB is −17 dBm at 30 GHz. [ABSTRACT FROM AUTHOR]

This paper proposes a 2.4-GHz fully-integrated single-frequency multi-channel RF energy harvesting (RFEH) system with increased harvested power density. The RFEH can produce an output power of ~423-μW in harvesting ambient RF energy. The front-end consists of an on-chip impedance matching network with a stacked rectifier concurrently matched to a 50 Ω input source. The circuit mitigates the "dead-zone" by enhancing the pumping efficiency, achieved through the increase of Vgs drivability of the proposed internal gate boosting 6-stage low-input voltage charge pump and the 5-stage shared-auxiliary-biasing ring-voltage-controlled-oscillator (VCO) integrated to improve the start-up. The RFEH system, simulated in 180-nm complementary metal–oxide–semiconductor (CMOS), occupies an active area of 1.02 mm2. Post-layout simulations show a peak power conversion efficiency(PCE) of 21.15%, driving a 3.3-kΩ load at an input power of 0 dBm and sensitivity of −14.1 dBm corresponding to an output voltage, Vout,RFEH of 1.25 V. [ABSTRACT FROM AUTHOR]

This paper presents a compact E-band power amplifier (PA) implemented in a 40 nm CMOS process. The neutralization technique is adopted to improve reverse isolation, stability and power gain. The linearity of the PA is improved by operating the output stage in the deep class-AB region. Transformer-based matching networks (TMNs) are used for impedance transformation, and optimized for output power and efficiency. At 81 GHz, the presented PA achieves a maximum output 1 dB compressed power (P1dB) of 11.2 dBm and a saturated output power (Psat) of 12.7 dBm with 1 V supply. The power-added efficiencies at P1dB (PAE1dB) and 6 dB power back-off (PBO) are 15.6% and 6.5%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a Ku-band transmit and receive IC in 0.13 µm CMOS technology for mobile satellite communication beamforming systems. A Ku-band transmit and receive IC is composed of a bi-directional amplifier, a 6-bit phase shifter, and a 6-bit digital step attenuator. The precise trimming bits are implemented in the phase shifter (2.8°) and digital step attenuator (0.5 and 1 dB) for the amplitude and phase error correction. The phase variation range of the phase shifter is 360° with a phase resolution of 5.625°. The attenuation range of 31.5 dB with an amplitude resolution of 0.5 dB is achieved. The gain of 2~5 dB and the input/output return losses of >10 dB are achieved from 12 to 16 GHz. The chip size is 2.5 × 1.5 mm2 including bonding pads. The DC power consumption is 216 mW. [ABSTRACT FROM AUTHOR]

This paper presents a low-noise amplifier (LNA) with single to differential conversion (Balun) for multi-standard radio applications. The proposed LNA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage to cancel the noise and distortion of the CG stage. Using the proposed technique, a low noise figure (NF) is achieved while providing a wideband of operation. Furthermore, a feedback connection from the CS stage to the gate of the CG is employed to boost the transconductance of the CG stage ( g m C G ), and an additional complementary transistor is applied at the CS stage using current reuse to increase the overall transconductance of the CS stage ( g m C S ) without increasing the power consumed by the stage. This LNA was designed using TSMC 65 nm technology, and post-layout simulation results show operation across 0.5–5 GHz, a maximum power gain of 20 dB, 4 dB minimum NF, and third-order intercept point (IIP3) of −10 dBm while consuming only 5 mW of power from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

This paper analyzes the usefulness of approximate addition for digital image compression. Discrete Cosine Transform (DCT) is an important operation in digital image compression. We used accurate addition and approximate addition individually while calculating the DCT to perform image compression. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders individually. The accurate adder and approximate adders were implemented in an application specific integrated circuit (ASIC)-type design environment using a 32–28 nm complementary metal oxide semiconductor (CMOS) standard cell library and in a field programmable gate array (FPGA)-based design environment using a Xilinx Artix-7 device. Error analysis was performed to calculate the error parameters of various approximate adders by applying one million random input vectors. It is observed that the approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design parameters compared to the accurate adder. For an ASIC-type implementation using standard cells, an optimum approximate adder achieved 27.1% reduction in delay, 46.4% reduction in area, and 50.3% reduction in power compared to a high-speed accurate carry look-ahead adder. With respect to an FPGA-based implementation, an optimum approximate adder achieved 8% reduction in delay and 19.7% reduction in power while requiring 47.6% fewer look-up tables (LUTs) and 42.2% fewer flip-flops compared to the native accurate FPGA adder. [ABSTRACT FROM AUTHOR]

This paper presents newly developed two high-precision CMOS proximity capacitance image sensors: Chip A with 12 μm pitch pixels with a large detection area of 1.68 cm2; Chip B with 2.8 μm pitch 1.8 M pixels for a higher resolution. Both fabricated chips achieved a capacitance detection precision of less than 100 zF (10−19 F) at an input voltage of 20 V and less than 10 zF (10−20 F) at 300 V due to the noise cancelling technique. Furthermore, by using multiple input pulse amplitudes, a capacitance detection dynamic range of up to 123 dB was achieved. The spatial resolution improvement was confirmed by the experimentally obtained modulation transfer function for Chip B with various line and space pattens. The examples of capacitance imaging using the fabricated chips were also demonstrated. [ABSTRACT FROM AUTHOR]

Deep-brain stimulation (DBS) is an emerging research topic aiming to improve the quality of life of patients with brain diseases, and a great deal of effort has been focused on the development of implantable devices. This paper presents a low-noise amplifier (LNA) for the acquisition of biopotentials on DBS. This electronic module was designed in a low-voltage/low-power CMOS process, targeting implantable applications. The measurement results showed a gain of 38.6 dB and a −3 dB bandwidth of 2.3 kHz. The measurements also showed a power consumption of 2.8 μW. Simulations showed an input-referred noise of 6.2 μVRMS. The LNA occupies a microdevice area of 122 μm × 283 μm, supporting its application in implanted systems. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a low-loss and high-linearity DC-38 GHz CMOS SPDT switch for 5G multi-band communications in 0.18 μm CMOS. Traveling-wave matching (CLCL network) is used for the output-port (ports 2 and 3) matching and isolation enhancement, while π-matching (CLC matching) is adopted for the input-port (port 1) matching. Positive/negative gate-bias is adopted for linearity enhancement because larger Pin (i.e., AC signal with larger negative Vin) is required to conduct the off-state series switch transistor. Negative-body bias is used for insertion-loss reduction because the off-state series switch transistor is closer to an open state. The SPDT switch achieves insertion loss of 0.4–1.4 dB, 3.6–4.3 dB, and 4.5–5.9 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. Moreover, the SPDT switch achieves isolation of 37.5–59.4 dB, 25.7–28.7 dB, and 24.3–25.2 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. At 28 GHz, the SPDT switch achieves remarkable input 1-dB compression point (IP1dB) of 25.6 dBm, close to the simulated one (28 dBm). To the authors' knowledge, this is one of the best IP1dB results ever reported for millimeter-wave (mm-wave) SPDT switches. [ABSTRACT FROM AUTHOR]

For Convolutional Neural Networks (CNNs), Depthwise Separable CNN (DSCNN) is the preferred architecture for Application Specific Integrated Circuit (ASIC) implementation on edge devices. It benefits from a multi-mode approximate multiplier proposed in this work. The proposed approximate multiplier uses two 4-bit multiplication operations to implement a 12-bit multiplication operation by reusing the same multiplier array. With this approximate multiplier, sequential multiplication operations are pipelined in a modified DSCNN to fully utilize the Processing Element (PE) array in the convolutional layer. Two versions of Approximate-DSCNN (A-DSCNN) accelerators were implemented on TSMC 40 nm CMOS process with a supply voltage of 0.9 V. At a clock frequency of 200 MHz, the designs achieve 4.78 GOPs/mW and 4.89 GOP/mW power efficiency while occupying 1.16 mm 2 and 0.398 mm 2 area, respectively. [ABSTRACT FROM AUTHOR]

With the extensive applications of biomagnetic signals derived from active biological tissue in both clinical diagnoses and human-computer-interaction, there is an increasing need for approachable weak biomagnetic sensing technology. The inherent merits of giant magnetoresistance (GMR) and its high integration with multiple technologies makes it possible to detect weak biomagnetic signals with micron-sized, non-cooled and low-cost sensors, considering that the magnetic field intensity attenuates rapidly with distance. This paper focuses on the state-of-art in integrated GMR technology for approachable biomagnetic sensing from the perspective of discipline fusion between them. The progress in integrated GMR to overcome the challenges in weak biomagnetic signal detection towards high resolution portable applications is addressed. The various strategies for 1/f noise reduction and sensitivity enhancement in integrated GMR technology for sub-pT biomagnetic signal recording are discussed. In this paper, we review the developments of integrated GMR technology for in vivo/vitro biomagnetic source imaging and demonstrate how integrated GMR can be utilized for biomagnetic field detection. Since the field sensitivity of integrated GMR technology is being pushed to fT/Hz0.5 with the focused efforts, it is believed that the potential of integrated GMR technology will make it preferred choice in weak biomagnetic signal detection in the future. [ABSTRACT FROM AUTHOR]

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low power hand gesture sensor using electrostatic induction for mobile devices. Two electrodes, which consist of electret foils stacked on metal sheets, are used to recognize two gestures such as hand movements from left to right and right to left. The hand gesture recognition is realized by detecting the electrostatic induction currents induced by hand movements. However, the electrostatic induction currents are significantly small; hence, a hand gesture recognition chip is first designed in this study to amplify and detect the small electrostatic induction currents with low power. This chip is fabricated in a commercial 180 nm complementary metal oxide semiconductor (CMOS) process, and the measurement results indicate that the fabricated gesture recognition chip consumes 406 nW, which is less than 1/100th of the power dissipation of conventional gesture sensors. [ABSTRACT FROM AUTHOR]

Nuclear Magnetic Resonance (NMR) is a non-contact, powerful structure-elucidation technique for biochemical analysis. NMR spectroscopy is used extensively in a variety of life science applications including drug discovery. However, existing NMR technology is limited in that it cannot run a large number of experiments simultaneously in one unit. Recent advances in micro-fabrication technologies have attracted the attention of researchers to overcome these limitations and significantly accelerate the drug discovery process by developing the next generation of high-throughput NMR spectrometers using Complementary Metal Oxide Semiconductor (CMOS). In this paper, we examine this paradigm shift and explore new design strategies for the development of the next generation of high-throughput NMR spectrometers using CMOS technology. A CMOS NMR system consists of an array of high sensitivity micro-coils integrated with interfacing radio-frequency circuits on the same chip. Herein, we first discuss the key challenges and recent advances in the field of CMOS NMR technology, and then a new design strategy is put forward for the design and implementation of highly sensitive and high-throughput CMOS NMR spectrometers. We thereafter discuss the functionality and applicability of the proposed techniques by demonstrating the results. For microelectronic researchers starting towork in the field of CMOSNMR technology, this paper serves as a tutorialwith comprehensive review of state-of-the-art technologies and their performance levels. Based on these levels, the CMOS NMR approach offers unique advantages for high resolution, time-sensitive and high-throughput bimolecular analysis required in a variety of life science applications including drug discovery. [ABSTRACT FROM AUTHOR]

This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. [ABSTRACT FROM AUTHOR]

Silicon-based Hall application-specific integrated circuit (ASIC) chips have become very successful, making them ideal for flexible electronic and sensor devices. In this study, we designed, simulated, and tested flexible hybrid integration angle sensors that can be made using complementary metal-oxide-semiconductor (CMOS) technology. These sensors are manufactured on a 100 µm-thick flexible polyimide (PI) membrane, which is suitable for large-scale production and has strong potential for industrial use. The Hall sensors have a sensitivity of 0.205 V/mT. Importantly, their sensitivity remains stable even after being bent to a minimum radius of 10 mm and after undergoing 100 bending cycles. The experiment shows that these flexible hybrid integration devices are promising as angle sensors. [ABSTRACT FROM AUTHOR]

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 µW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. [ABSTRACT FROM AUTHOR]

Movable suspended microstructures are the common feature of sensors or devices in the fields of Complementary-Metal-Oxide-Semiconductors and Micro-Electro-Mechanical Systems which are usually abbreviated as CMOS-MEMS. To suspend the microstructures, it is commonly to etch the sacrificial layer under the microstructure layer. For large-area microstructures, it is necessary to design a large number of etching holes on the microstructure to enhance the etchant uniformly and rapidly permeate into the sacrificial layer. This paper aims at evaluating the fringe capacitance caused by etching holes on microstructures and developing empirical formulas. The formula of capacitance compensation term is derived by curve-fitting on the simulation results by the commercial software ANSYS. Compared with the ANSYS simulation, the deviation of the present formula is within ±5%. The application to determine the capacitance of an electrostatic micro-beam with etching holes is demonstrated in a microstructure experiment, which agrees very well with the experimental data, and the maximum deviation is within ±8%. The present formula is with simple form, wide application range, high accuracy, and easy to use. It is expected to provide the micro-device designers to estimate the capacitance of microstructures with etching holes and predominate in the device characteristics. [ABSTRACT FROM AUTHOR]

Recent advances in integrated biosensors, wireless communication and power harvesting techniques are enticing researchers into spawning a new breed of point-of-care (POC) diagnostic devices that have attracted significant interest from industry. Among these, it is the ones equipped with wireless capabilities that drew our attention in this review paper. Indeed, wireless POC devices offer a great advantage, that of the possibility of exerting continuous monitoring of biologically relevant parameters, metabolites and other bio-molecules, relevant to the management of various morbid diseases such as diabetes, brain cancer, ischemia, and Alzheimer's. In this review paper, we examine three major categories of miniaturized integrated devices, namely; the implantable Wireless Bio-Sensors (WBSs), the wearable WBSs and the handheld WBSs. In practice, despite the aforesaid progress made in developing wireless platforms, early detection of health imbalances remains a grand challenge from both the technological and the medical points of view. This paper addresses such challenges and reports the state-of-the-art in this interdisciplinary field. [ABSTRACT FROM AUTHOR]

In this paper,we share our practical experience gained during the development ofCMOS-MEMS (ComplementaryMetal-Oxide Semiconductor Micro Electro Mechanical Systems) devices in IHP SG25 technology. The experimental prototyping process is illustrated with examples of three CMOS-MEMS chips and starts from rough process exploration and characterization, followed by the definition of the useful MEMS design space to finally reach CMOS-MEMS devices with inertial mass up to 4.3 μg and resonance frequency down to 4.35 kHz. Furthermore, the presented design techniques help to avoid several structural and reliability issues such as layer delamination, device stiction, passivation fracture or device cracking due to stress. [ABSTRACT FROM AUTHOR]

Recently, studies have been actively carried out to implement motion detecting sensors by applying radar techniques. Doppler radar or frequency-modulated continuous wave (FMCW) radar are mainly used, but each type has drawbacks. In Doppler radar, no signal is detected when the movement is stopped. Also, FMCW radar cannot function when the detection object is near the sensor. Therefore, by implementing a single continuous wave (CW) radar for operating in dual-mode, the disadvantages in each mode can be compensated for. In this paper, a dual mode local oscillator (LO) is proposed that makes a CW radar operate as a Doppler or FMCW radar. To make the dual-mode LO, a method that controls the division ratio of the phase locked loop (PLL) is used. To support both radar mode easily, the proposed LO is implemented by adding a frequency sweep generator (FSG) block to a fractional-N PLL. The operation mode of the LO is determined by according to whether this block is operating or not. Since most radar sensors are used in conjunction with microcontroller units (MCUs), the proposed architecture is capable of dual-mode operation by changing only the input control code. In addition, all components such as VCO, LDO, and loop filter are integrated into the chip, so complexity and interface issues can be solved when implementing radar sensors. Thus, the proposed dual-mode LO is suitable as a radar sensor. [ABSTRACT FROM AUTHOR]

This work presents an on-chip 60 GHz lumped element transmission line (TL) using cascaded T-networks with a high Quality factor. Each T-network consists of a series inductance with a shunt capacitance at its center. We have derived the design equations for this TL configuration and proved that a TL whose electrical length ≥ 60° achieves additional miniaturization when implemented with three or more cascaded T-networks. The inductance is implemented using a straight wire model with no ground below it, while the capacitance is implemented using a parallel plate model with a grounding pedestal. Both configurations guarantee maximum inductance per unit length and capacitance per unit area to further improve the miniaturization level. A quarter wavelength TL with three cascaded T-networks is fabricated as proof of concept. The measured and simulated results of the fabricated TL have good agreement, and the measured quality factor is 17 at 60 GHz. [ABSTRACT FROM AUTHOR]

Extreme ultraviolet lithography (EUVL) is a leading technology in semiconductor manufacturing, enabling the creation of high-resolution patterns essential for advanced microelectronics. This review highlights recent progress in inorganic metal-oxide-based photoresists, with a focus on their applications in EUVL. The unique properties of zinc-based, tin–oxygen, and IVB group inorganic photoresists are examined, showcasing their enhanced chemical reactivity and precise patterning capabilities. Key advancements include the development of zinc oxide and tin oxide nanoparticles, which demonstrate significant improvements in photon absorption and solubility under extreme ultraviolet exposure. Additionally, the review delves into the photochemical reactions of tin–oxygen clusters and the influence of various ligands on film density and cross-linking. The findings suggest that these inorganic photoresists not only improve photolithographic performance but also hold potential for broader applications, such as pyroelectric infrared sensors and 3D printing. Future research directions are outlined, including the optimization of process parameters, the exploration of new ligand and metal combinations, and the evaluation of the environmental benefits of inorganic photoresists over traditional organic ones. These advancements are poised to further enhance the resolution and patterning capabilities required for next-generation semiconductor devices. [ABSTRACT FROM AUTHOR]

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application. [ABSTRACT FROM AUTHOR]

This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm² in a 0.35-µm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 µW at a sample rate of 10 samples/s. [ABSTRACT FROM AUTHOR]

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps). [ABSTRACT FROM AUTHOR]

In this paper, guidelines for the optimization of piezoelectrical micromachined ultrasound transducers (PMUTs) monolithically integrated over a CMOS technology are developed. Higher acoustic pressure is produced by PMUTs with a thin layer of AlN piezoelectrical material and Si3N4 as a passive layer, as is studied here with finite element modeling (FEM) simulations and experimental characterization. Due to the thin layers used, parameters such as residual stress become relevant as they produce a buckled structure. It has been reported that the buckling of the membrane due to residual stress, in general, reduces the coupling factor and consequently degrades the efficiency of the acoustic pressure production. In this paper, we show that this buckling can be beneficial and that the fabricated PMUTs exhibit enhanced performance depending on the placement of the electrodes. This behavior was demonstrated experimentally and through FEM. The acoustic characterization of the fabricated PMUTs shows the enhancement of the PMUT performance as a transmitter (with 5 kPa V−1 surface pressure for a single PMUT) and as a receiver (12.5 V MPa−1) in comparison with previously reported devices using the same MEMS-on-CMOS technology as well as state-of-the-art devices. [ABSTRACT FROM AUTHOR]

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices. [ABSTRACT FROM AUTHOR]

This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW. [ABSTRACT FROM AUTHOR]

In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID) measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail. Original array sensors were suggested and fabricated that allowed high statistical significance of the radiation measurements and radiation imaging functions. Single sensors and array sensors were analyzed in combination with the specially developed test structures. This allowed insight into the physics of sensor operations and exclusion of the phenomena related to material degradation under irradiation in the interpretation of the measurement results. Response of the developed sensors to various sources of ionizing radiation (Gamma, X-ray, UV, energetic ions) was investigated. The optimal design of sensor for implementation in dosimetry systems was suggested. The roadmap for future improvement of sensor performance is suggested. [ABSTRACT FROM AUTHOR]

This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation. [ABSTRACT FROM AUTHOR]

This paper reports a "single-transistor" Class-F−1 power amplifier (PA) in 65 nm CMOS, which operates at the microwave center frequency of 6 GHz. The PA is loaded with a Class-F−1 harmonic control network, employing a new "parasitic-aware" topology deduced using a novel iterative algorithm. A dual-purpose output matching network is designed, which not only serves the purpose of output impedance matching, but also reinforces the harmonic control of the Class-F−1 harmonic network. This proposed PA yields a peak power-added efficiency (PAE) of 47.8%, which is one of the highest when compared to previously reported integrated microwave/millimeter-wave PAs in CMOS and SiGe technologies. The amplifier shows a saturated output power of 14.4 dBm along with an overall gain of 13.8 dB. [ABSTRACT FROM AUTHOR]

The basic need common to all living beings is water. Less than 1% of the water on earth is fresh water and water use is increasing daily. Agricultural practices alone require huge amounts of water. The drip technique improved the efficiency of water use in irrigation and initiated the introduction and development of fertigation, the integrated distribution of water and fertilizer. The past few decades have seen extensive research being carried out in the area of development and evaluation of different technologies available to estimate/measure soil moisture to aid in various applications and to facilitate the use of drip irrigation for users and farmers. In this technology, plant moisture and temperature are accurately monitored and controlled in real time over roots in the form of droplets, by developing smart monitoring system to save water and avoid water waste using drip irrigation technology. Water is delivered to the roots drop by drop, which saves water as well as prevents plants from being flooded and decaying due to excess water released by irrigation methods such as flood irrigation, border irrigation, furrow irrigation, and control basin irrigation. Drip irrigation with an embedded intelligent monitoring system is one of the most valuable techniques used to save water and farmers' time and energy. In this paper, we design an embedded monitoring system based in the integrated 65 nm CMOS technology in agricultural practices which would facilitate agriculture and enable farmers to monitor crops. Hence, to demonstrate the feasibility, a prototype was constructed and simulated with modelsim and validated with nclaunch the both tools from Cadence, as well as implementation on the FPGA board, was be performed. [ABSTRACT FROM AUTHOR]

This work presents two Wilkinson power dividers (WPDs) using multi-layer pseudo coplanar waveguide (PCPW) structures. The PCPW-based WPDs were designed, implemented, and verified in a standard 180 nm CMOS process. The proposed PCPW features high slow-wave and low-loss performances compared to other common transmission lines. The two WPDs are based on the same PCPW structure parameters in terms of line width, spacing, and used metal layers. One WPD was realized in a straight PCPW-based layout, and the other WPD was realized in a meandered PCPW-based layout. Both the two WPDs worked up to V-band frequencies, as expected, which also demonstrates that the PCPW guiding structure is less susceptible to the effects of meanderings on the propagation constant and characteristic impedance. The meandered design shows that the measured insertion losses were about 5.1 dB, and its return losses were better than 17.5 dB at 60 GHz. In addition, its isolation, amplitude imbalance, and phase imbalance were 18.5 dB, 0.03 dB, and 0.4°, respectively. The core area was merely 0.2 mm × 0.23 mm, or 1.8 × 10−3λo2. [ABSTRACT FROM AUTHOR]

To translate near-infrared (NIR) and shortwave infrared (SWIR) fluorescence imaging into the clinic, the paired imaging device needs to detect trace doses of fluorescent imaging agents. Except for the filtration scheme and excitation light source, the image sensor used will finally determine the detection limitations of NIR and SWIR fluorescence imaging systems. In this review, we investigate the current state-of-the-art image sensors used in NIR and SWIR fluorescence imaging systems and discuss the advantages and limitations of their characteristics, such as readout architecture and noise factors. Finally, the imaging performance of these image sensors is evaluated and compared. [ABSTRACT FROM AUTHOR]

A Point-of-Care system for molecular diagnosis (PoC-MD) is described, combining GaN and CMOS chips. The device is a micro-system for fluorescence measurements, capable of analyzing both intensity and lifetime. It consists of a hybrid micro-structure based on a 32 × 32 matrix addressable GaN microLED array, with square LEDs of 50 µm edge length and 100 µm pitch, with an underneath wire bonded custom chip integrating their drivers and placed face-to-face to an array of 16 × 16 single-photon avalanche diodes (SPADs) CMOS. This approach replaces instrumentation based on lasers, bulky optical components, and discrete electronics with a full hybrid micro-system, enabling measurements on 32 × 32 spots. The reported system is suitable for long lifetime (>10 ns) fluorophores with a limit of detection ~1/4 µM. Proof-of-concept measurements of streptavidin conjugate Qdot™ 605 and Amino PEG Qdot™ 705 are demonstrated, along with the device ability to detect both fluorophores in the same measurement. [ABSTRACT FROM AUTHOR]

An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver. [ABSTRACT FROM AUTHOR]