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This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of −7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm. [ABSTRACT FROM AUTHOR]

This paper presents a small-size broadband slot monopole chip antenna for millimeter wave application. Using a 0.18 μm CMOS process, through metal_1, the artificial magnetic conductor (AMC) of the metal layer increased the impedance bandwidth of the chip antenna. The additional inverted C branch was used to achieve a better reflection coefficient. By adding an AMC and inverted C branch, the operating frequency of the chip antenna went to 33.8–110 GHz below the reflection coefficient of −10 dB, and its fractional bandwidth was 103.4%. The maximum gain was −6.3 dBi at 72 GHz. The overall chip size was 1.2 × 1.2 (mm2). Through measurement and verification, the proposed antenna reflection coefficient was close to the simulation trend and had better resonance. The frequency range of the chip antenna proposed in this paper covered the 5G NR FR2 band (24.2 GHz–52.6 GHz) and W-band (75 GHz–110 GHz). The proposed chip antenna can be applied to the Internet of Things, Industry 4.0, biomedical electronics, near field sensing and other related fields. [ABSTRACT FROM AUTHOR]

This paper introduces an innovative method for the analysis of alcohol–water droplets on a CMOS capacitive sensor, leveraging the controlled thermal behavior of the droplets. Using this sensing method, the capacitive sensor measures the total time of evaporation (ToE), which can be influenced by the droplet volume, temperature, and chemical composition. We explored this sensing method by introducing binary mixtures of water and ethanol or methanol across a range of concentrations (0–100%, with 10% increments). The experimental results indicate that while the capacitive sensor is effective in measuring both the total ToE and dielectric properties, a higher dynamic range and resolution are observed in the former. Additionally, an array of sensing electrodes successfully monitors the droplet–sensor surface interaction. However practical considerations such as the creation of parasitic capacitance due to mismatch, arise from the large sensing area in the proposed capacitive sensors and other similar devices. In this paper, we discuss this non-ideality and propose a solution. Also, this paper showcases the benefits of utilizing a CMOS capacitive sensing method for accurately measuring ToE. [ABSTRACT FROM AUTHOR]

This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents the design and the performance of a wide tuning-range millimeter-wave (mm-wave) two-core class-C 60 GHz VCO in 40 nm CMOS process, which can be integrated into wireless communication transceivers and radar sensors. The proposed architecture consists of a two-core 30 GHz fundamental VCO, a gain-boosted frequency doubler and an adaptive bias configuration. The two-core fundamental VCO structure achieves frequency generation in the vicinity of 30 GHz, where each VCO core targets a different frequency band. The two bands have sufficient overlap to accommodate for corner variations providing a large continuous tuning range. The desired frequency band is selected by activating or deactivating the appropriate VCO core, resulting in a robust switchless structure. This approach enables a considerably broad tuning range without compromising phase noise performance. Furthermore, the proposed topology utilizes an adaptive bias mechanism for robust start-up. Initially, the selected VCO core begins oscillating in class-B mode, and subsequently it transitions into class-C operation to offer improved performance. From post-layout simulations, after frequency doubling, the low-band VCO covers frequencies from 50.25 to 60.40 GHz, while the high-band VCO core spans frequencies from 58.8 to 73 GHz, yielding an overall tuning range of 36.92%. Owing to the gain-boosting topology, output power exceeds −14.2 dBm across the whole bandwidth. Simulated phase noise remains better than −92.1 dBc/Hz at a 1 MHz offset for all bands. Additionally, the two VCO cores never operate simultaneously, aiding in power efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a low power wideband dB-linear analog baseband (ABB) circuit for a millimeter-wave (mmW) wireless receiver in 40 nm CMOS technology. The proposed ABB system consists of a multi-stage variable gain amplifier (VGA) and a low-pass filter (LPF). The 5-stage VGA is composed of two variable gain units followed by three fixed gain units with DC offset cancellation (DCOC). The first variable gain unit with a self-compensated transistor pair and compact active inductor load is designed for dB-linear functionality and bandwidth extension, respectively. Moreover, a proposed error compensation method is applied to the second cascaded variable gain unit for further dB-linear gain error correction. A 4th-order Butterworth transconductance-capacitance (Gm-C) LPF with flipped source follower (FSF) as an input transconductance stage for linearity enhancement is designed after the VGA stage. The prototype chip is implemented, and measurement results show a dB-linear gain range from −18 to 26 dB with less than 0.5 dB-linear gain error with a bandwidth of 4 GHz. The VGA and LPF consume 8.3 mW and 3 mW, respectively, under a 1 V power supply, while the entire ABB occupies an area of 0.94 mm2 with an active core area of only 0.045 mm2. [ABSTRACT FROM AUTHOR]

The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, designing robust SRAM cells that maintain stability and minimize power consumption is a key challenge. In this regard, with this ongoing work, the authors present novel designs of SRAMs using memristor technology by mitigating the shortcomings discussed above. This paper proposes a novel SRAM architecture of four transistors and five memristors, by integrating memristor technology to achieve drastic improvement in performance at subthreshold regions. Further, it performs an analysis of the metrics of static noise margin and power consumption to comprehensively evaluate the proposed SRAM designs. Simulation using Cadence Virtuoso for 65 nm technology demonstrates that power consumption for a 4T5M cell is about two and a half times lower than for 4T4M and 1.2 times lower than for 4T3M, hence proving that it will be promising for extremely low-power applications. [ABSTRACT FROM AUTHOR]

Voltage reference circuits are a basic building block in most integrated microsystems, covering a wide spectrum of applications. Hence, they constitute a subject of great interest for the entire microelectronics community. MOSFET-based solutions, in particular, have emerged as the implementation of choice for realizing voltage reference circuits, given the supply voltage scaling and the ever-lower power consumption specifications in various applications. For these reasons, this paper aims to review MOSFET-based voltage reference circuits, illustrating their principles of operation, as well as presenting a detailed overview of the state-of-the-art, in order to paint an accurate picture of the encountered challenges and proposed solutions found in the field in the last decade, thus providing a starting point for future research in the field. [ABSTRACT FROM AUTHOR]

The traditional Von Neumann architecture creates bottlenecks due to data movement. The compute-in-memory (CIM) architecture performs computations within memory bit-cell arrays, enhancing computational performance. Edge devices utilizing artificial intelligence (AI) address real-time problems and have established themselves as groundbreaking technology. The 8T structure proposed in this paper has strengths over other existing structures in that it better withstands environmental changes within the SRAM and consumes lower power during memory operation. This structure minimizes reliance on complex ADCs, instead utilizing a simplified voltage differential approach for multiply-and-accumulate (MAC) operations, which enhances both power efficiency and stability. Based on these strengths, it can achieve higher battery efficiency in AI edge devices and improve system performance. The proposed integrated circuit was simulated in a 90 nm CMOS process and operated on a 1 V supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, we present a high power-added efficiency (PAE) and high gain per stage 60 GHz power amplifier (PA). The proposed PA consists of a two-stage common-source amplifier that incorporates neutralization capacitors and compensation inductors to enhance both gain and efficiency. The gain characteristics are analyzed, demonstrating that the proposed design improves both gain and efficiency. Implemented in 65 nm CMOS technology, the PA achieves a saturated output power of 13.4 dBm at 60 GHz, with a maximum PAE of 26.7% from a 1 V supply. The output 1 dB compression point is 10.5 dBm, with a PAE of 16%. The PA occupies a core chip area of 0.094 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a Doherty power amplifier (DPA) integrated circuit (IC) designed to have enhanced gain, efficiency, and AM-AM characteristics through a dynamic power dividing technique, which can control the power dividing ratio according to the input power. Since this multi-purpose dynamic power dividing network also provides the phase offset and impedance matching at the interstage network needed for appropriate DPA operation, the active IC area could be reduced. To verify the proposed technique and its analysis, the DPA was implemented with a 28 nm bulk CMOS process for the fifth-generation (5G) new radio (NR) millimeter-wave frequency band of 23.5–27.5 GHz. The measured results showed a gain of 20.3–21.9 dB, saturated output power of 14.0–15.2 dBm, power added efficiency (PAE) of 22.8–26.7% at the peak power, and PAE of 14.6–17.6% at the 6 dB output power back-off (OBO). [ABSTRACT FROM AUTHOR]

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field. [ABSTRACT FROM AUTHOR]

This paper presents an 8 × 8 channel optoelectronic readout array (ORA) realized in the TSMC 180 nm 1P6M RF CMOS process for the applications of short-range light detection and ranging (LiDAR) sensors. We propose several circuit techniques in this work, including an amplitude-to-voltage (A2V) converter that reduces the notorious walk errors by intensity compensation and a time-to-voltage (T2V) converter that acquires the linear slope of the output signals by exploiting a charging circuit, thus extending the input dynamic range significantly from 5 μApp to 1.1 mApp, i.e., 46.8 dB. These results correspond to the maximum detection range of 8.2 m via the action of the A2V converter and the minimum detection range of 56 cm with the aid of the proposed T2V converter. Optical measurements utilizing an 850 nm laser diode confirm that the proposed 8 × 8 ORA with 64 on-chip avalanche photodiodes (APDs) can successfully recover the narrow 5 ns light pulses even at the shortest distance of 56 cm. Hence, this work provides a potential CMOS solution for low-cost, low-power, short-range LiDAR sensors. [ABSTRACT FROM AUTHOR]

Optical and magnetic sensing methods are integral to both research and clinical applications in biological laboratories. The ongoing miniaturization of these sensors has paved the way for the development of point-of-care (PoC) diagnostics and handheld sensing devices, which are crucial for timely and efficient healthcare delivery. Among the various competing sensing and circuit technologies, CMOS (complementary metal–oxide–semiconductor) stands out due to its distinct cost-effectiveness, scalability, and high precision. By leveraging the inherent advantages of CMOS technology, recent developments in optical and magnetic biosensors have significantly advanced their application in life sciences, offering improved sensitivity, integration capabilities, and reduced power consumption. This paper provides a comprehensive review of recent advancements, focusing on innovations in CMOS-based optical and magnetic sensors and their transformative impact on biomedical research and diagnostics. [ABSTRACT FROM AUTHOR]

With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel optoelectronic transimpedance amplifier (OTA) for short-range LiDAR sensors used in 180 nm CMOS technology, which consists of a main transimpedance amplifier (m-TIA) with an on-chip P+/N-well/Deep N-well avalanche photodiode (P+/NW/DNW APD) and a replica TIA with another on-chip APD, not only to acquire circuit symmetry but to also obtain concurrent automatic gain control (AGC) function within a narrow single pulse-width duration. In particular, for concurrent AGC operations, 3-bit PMOS switches with series resistors are added in parallel with the passive feedback resistor in the m-TIA. Then, the PMOS switches can be turned on or off in accordance with the DC output voltage amplitudes of the replica TIA. The post-layout simulations reveal that the OTA extends the dynamic range up to 74.8 dB (i.e., 1 µApp~5.5 mApp) and achieves a 67 dBΩ transimpedance gain, an 830 MHz bandwidth, a 16 pA/ √ Hz noise current spectral density, a −31 dBm optical sensitivity for a 10−12 bit error rate, and a 6 mW power dissipation from a single 1.8 V supply. The chip occupies a core area of 200 × 120 µm2. [ABSTRACT FROM AUTHOR]

This paper presents a novel power-efficient topology for receivers in short-range LiDAR sensors. Conventionally, LiDAR sensors exploit complex time-to-digital converters (TDCs) for time-of-flight (ToF) distance measurements, thereby frequently leading to intricate circuit designs and persistent walk error issues. However, this work features a fully differential trans-impedance amplifier with on-chip avalanche photodiodes as optical detectors so that the need of the following post-amplifiers and output buffers can be eliminated, thus considerably reducing power consumption. Also, the combination of amplitude-to-voltage (A2V) and time-to-voltage (T2V) converters are exploited to replace the complicated TDC circuit. The A2V converter efficiently processes weak input photocurrents ranging from 1 to 50 μApp which corresponds to a maximum distance of 22.8 m, while the T2V converter handles relatively larger photocurrents from 40 μApp to 5.8 mApp for distances as short as 30 cm. The post-layout simulations confirm that the proposed LiDAR receiver can detect optical pulses over the range of 0.3 to 22.8 m with a low power dissipation of 10 mW from a single 1.8 V supply. This topology offers significant improvements in simplifying the receiver design and reducing the power consumption, providing a more efficient and accurate solution that is highly suitable for short-range LiDAR sensor applications. [ABSTRACT FROM AUTHOR]

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter's frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing. [ABSTRACT FROM AUTHOR]

This paper presents an inverter-based active feedback transimpedance amplifier (IAF-TIA), in which an active feedback is applied to a voltage-mode inverter-based TIA, and therefore, the controlled positive regeneration process enables the proposed IAF-TIA to achieve the limiting operations for input currents greater than 100 μApp. However, the active inverter feedback mechanism might be prone to instability, hence mandating a very careful optimization of the loop gain. For this purpose, a diode-connected NMOS transistor is employed as a switch in the feedback path with its gate connected to the input, which helps not only to mitigate the corresponding issue but also to accommodate large input currents up to 1.5 mApp. The proposed IAF-TIA implemented in a standard 180 nm CMOS process demonstrates a 70.5 dBΩ transimpedance gain, 1.21 GHz bandwidth, 4.3   pA / Hz noise current spectral density, 63.5 dB input dynamic range, and 23.6 mW power dissipation from a single 1.8 V supply. The chip core occupies an area of 180 × 50 μm2, including an on-chip P+/N-well/Deep N-well avalanche photodiode as an optical detector. [ABSTRACT FROM AUTHOR]

In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency. [ABSTRACT FROM AUTHOR]

This paper presents a test methodology to facilitate the measuring processes of LiDAR receiver ICs by avoiding the inherent walk error issue. In a typical LiDAR system, a costly laser diode driver emits narrow light pulses with fast rising edges, and the reflected pulses from targets enter an optical detector followed by an analog front-end (AFE) circuit. Then, the received signals pass through the cascaded amplifiers down to the time-to-digital converter (TDC) that can estimate the detection range. However, this relatively long signal journey leads to the significant decline of rising-edge slopes and the output pulse spreading, thus producing inherent walk errors in LiDAR receiver ICs. Compensation methods requiring complex algorithms and extra chip area have frequently been exploited to lessen the walk errors. In this paper, however, a simpler and lower-cost methodology is proposed to test LiDAR receiver ICs by employing a high-speed buffer and variable delay cells right before the TDC. With these circuits, both START and STOP pulses show very similar pulse shapes, thus effectively avoiding the walk error issue. Additionally, the time interval between two pulses is easily determined by varying the number of the delay cells. Test chips of the proposed receiver IC implemented in a 180-nm CMOS process successfully demonstrate easier and more accurate measurement results. [ABSTRACT FROM AUTHOR]

This paper introduces a design for a charge pump DC-DC boost regulator with an integrated low-voltage control circuit. With a charge pump and feedback circuits implemented in 0.35 µm CMOS technology, the proposed DC-DC boost regulator offers an efficient device solution for low-power applications. The proposed design employs an error amplifier, oscillator, and comparator in the control circuit which is designed with a supply voltage of 1.8–3.5 V and 2 MHz frequency. Stability is obtained via a pole-zero compensation in the feedback circuit. The charge pump regulator with four pump stages and the whole regulator circuit are analyzed using the Cadence simulation tool. Measurements of the fabricated 0.35 µm CMOS regulator show that the transient time of the error amplifier is controlled within 1.0 µsec and the output voltage is accurately controlled from 7.8 V to 9.4 V with 27–38 mV ripple and 4.5 mA maximum current. [ABSTRACT FROM AUTHOR]

Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H. [ABSTRACT FROM AUTHOR]

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature. [ABSTRACT FROM AUTHOR]

In this paper, we present a highly linear direct in-phase/quadrature (I/Q) up-conversion mixer for 5G millimeter-wave applications. To enhance the linearity of the mixer, we propose a complementary derivative superposition technique with pre-distortion. The proposed up-conversion mixer consists of a quadrature generator, LO buffer amplifiers, and an I/Q up-conversion mixer core and achieves an output third-order intercept point of 15.7 dBm and an output 1 dB compression point of 2 dBm at 27.6 GHz, while it consumes 15 mW at a supply voltage of 1 V. The conversion gain is 11.4 dB and the LO leakage and image rejection ratio are −56 dBc and 61 dB, respectively, in the measurement. The proposed I/Q up-conversion mixer is suitable for 5G cellular communication systems. [ABSTRACT FROM AUTHOR]

This paper presents an automatic piecewise (Auto-PW) extreme learning machine (ELM) method for S-parameters modeling radio-frequency (RF) power amplifiers (PAs). A strategy based on splitting regions at the changing points of concave-convex characteristics is proposed, where each region adopts a piecewise ELM model. The verification is carried out with S-parameters measured on a 2.2–6.5 GHz complementary metal oxide semiconductor (CMOS) PA. Compared to the long-short term memory (LSTM), support vector regression (SVR), and conventional ELM modeling methods, the proposed method performs excellently. For example, the modeling speed is two orders of magnitude faster than SVR and LSTM, and the modeling accuracy is more than one order of magnitude higher than ELM. [ABSTRACT FROM AUTHOR]

This paper presents an overview of silicon-based optical sensors for the measurement of light in the visible spectrum range. The review is focused on sensors based on CMOS (complementary metal-oxide semiconductor) technology due to the high availability, low cost, ease of prototyping, and well-established fabrication processes. CMOS technology allows integration with the CMOS readout and control electronics in the same microdevice, featuring high-volume fabrication with high-reproducibility and low-cost. This review starts with an explanation of the phenomena behind opto-electronic transduction. It also presents and describes the most common components responsible for optical transduction, readout electronics, and their main characteristics. This review finishes with the presentation of selected applications to grasp where and how these sensors can be used. [ABSTRACT FROM AUTHOR]

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications. [ABSTRACT FROM AUTHOR]

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency. [ABSTRACT FROM AUTHOR]

This paper presents an electron multiplication charge coupled device (EMCCD) based on capacitive deep trench isolation (CDTI) and developed using complementary metal oxide semiconductor (CMOS) technology. The CDTI transfer register offers a charge transfer inefficiency lower than 10 − 4 and a low dark current o 0.11 nA / cm 2 at room temperature. In this work, the timing diagram is adapted to use this CDTI transfer register in an electron multiplication mode. The results highlight some limitations of this device in such an EM configuration: for instance, an unexpected increase in the dark current is observed. A design modification is then proposed to overcome these limitations and rely on the addition of an electrode on the top of the register. Thus, this new device preserves the good transfer performance of the register while adding an electron multiplication function. Technology computer-aided design (TCAD) simulations in 2D and 3D are performed with this new design and reveal a very promising structure. [ABSTRACT FROM AUTHOR]

The specification of power amplifiers (PA) is closely related to humidity variation, and few reports on the humidity properties of PA are available in the literature. Therefore, an experimental study of PA specifications was conducted under different humidity conditions to elucidate the relationship between the degradation of PA specifications and humidity conditions. This paper studies and provides results of the degradation of a PA subjected to different humidity levels. The experimental results show that the S21 and output power decrease with the increase in humidity. The main cause of this degradation is the decrease in oxide capacitance and increase in threshold voltage with increasing humidity, resulting in a reduction of transconductance and an increase in on-resistance. The results of this study can guide designers in designing compensation circuits to achieve some degree of compensation for the degradation of PA specifications. [ABSTRACT FROM AUTHOR]

To investigate the critical specifications of a power amplifier (PA) under rapidly changing temperature conditions, we fabricated and tested a 0.3–1.1 GHz complementary metal–oxide–semiconductor (CMOS) PA under thermal shock tests. The results show that high- and low-temperature shocks can accelerate the degradation of critical specifications of PAs and that the critical specifications of PAs degrade with the increasing number of shocks. The main reason for the degradation of critical specifications of PAs with increasing thermal shock tests is the mismatch of thermal expansion coefficients of printed circuit boards (PCB) with FR-4 as a substrate. The results of this paper can provide a reference for the development of temperature-robust PAs design guidelines for the implementation of temperature-robust PAs using low-cost silicon technology. [ABSTRACT FROM AUTHOR]

With the specialization of VLSI ASICs for front-end signal processing electronics, the customization of the control back-end electronics (BEE) has become critical to fully deploy the ASIC performance. In the context of space operations, with typical constraints on power and reliability, the design and qualification of such integrated systems present significant challenges. In this paper, we review the design and performance of the BEE systems after two years of operations in low Earth orbit (LEO); these systems read out the custom ASICs inside the gas pixel detectors, which are located at the heart of the imaging X-ray polarimetry explorer (IXPE), a NASA-ASI small explorer mission designed to measure X-ray polarization in the 2–8 keV energy range. [ABSTRACT FROM AUTHOR]

An Auto-Trimming CMOS Bandgap References Circuit (ATBGR) with PSRR enhancement circuit for Artificial Intelligence of Things (AIoT) chips is presented in this paper. The ATBGR is designed with a first-order temperature compensation technique providing a stable reference voltage of 1.25 V in the ranges of input voltages from 1.65 V to 4.5 V. An auto-trimming circuit is integrated into a PTAT resistor of BGR to minimize the influences of the process variations. The four parallel resistor pairs with PMOS switches are connected in series with the PTAT resistor. The reference voltage, VREF, is compared to an external constant value, 1.25 V, through an operational amplifier, and the output of the de-multiplexer is used to configure the PMOS switches. High power supply rejection is achieved through a PSRR enhancement circuit constituting a cascaded PMOS common gate pair. The ATBGR circuit is fabricated in 180 nm CMOS technology, consuming an area of 0.03277 mm2. The auto-trimming method yields an average temperature coefficient of 9.99 ppm/°C with temperature ranges from −40 °C to 125 °C, and a power supply rejection ratio of −90 dB at 100 MHz is obtained. The line regulation of the proposed circuit is 0.434%/V with power consumption of 54.12 µW at room temperature. [ABSTRACT FROM AUTHOR]

Wireless communication systems have undergone significant development in recent years, particularly with the transition from fourth generation (4G) to fifth generation (5G). As the number of wireless devices and mobile data usage increase, there is a growing need for enhancements and upgrades to the current wireless communication systems. CMOS transceivers are increasingly being explored to meet the requirements of the latest wireless communication protocols and applications while achieving the goal of system-on-chip (SoC). The radio frequency power amplifier (RFPA) in a CMOS transmitter plays a crucial role in amplifying RF signals and transmitting them from the antenna. This state-of-the-art review paper presents a concise discussion of the performance metrics that are important for designing a CMOS PA, followed by an overview of the trending research on CMOS PA techniques that focuses on efficiency, linearity, and bandwidth enhancement. [ABSTRACT FROM AUTHOR]

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and circuit designs. In this work, the SNN has been constituted from the analog neuron and synaptic circuits, which are designed to optimize both the chip area and power consumption. The proposed synapse circuit is based on a current multiplier charge injector (CMCI) circuit, which can significantly reduce power consumption and chip area compared with the previous work while allowing for design scalability for higher resolutions. The proposed neuron circuit employs an asynchronous structure, which makes it highly sensitive to input synaptic currents and enables it to achieve higher energy efficiency. To compare the performance of the proposed SoC in its area and power consumption, we implemented a digital SoC for the same SNN model in FPGA. The proposed SNN chip, when trained using the MNIST dataset, achieves a classification accuracy of 96.56%. The presented SNN chip has been implemented using a 65 nm CMOS process for fabrication. The entire chip occupies 0.96 mm2 and consumes an average power of 530 μW, which is 200 times lower than its digital counterpart. [ABSTRACT FROM AUTHOR]

This paper presents three different types of on-chip avalanche photodiodes (APDs) realized in a TSMC 180 nm 1P6M RF CMOS process, i.e., a P+/N-well (NW) APD for its high responsivity and large bandwidth by excluding slow diffusion currents; a P+/Deep N-well (DNW) APD for its improved near-infrared (NIR) sensitivity; and a P+/NW/DNW APD for its capability to prevent premature edge breakdown and improve NIR sensitivity. Thereafter, a conventional voltage-mode optoelectronic receiver (V-OER) was realized to confirm the feasibility of the three on-chip APDs. However, the measured results of the V-OER demonstrate a very narrow dynamic range. Therefore, we propose a current-mode optoelectronic receiver (C-OER) realized in the same CMOS process for the applications of short-range LiDAR sensors, where current-conveyor input buffers are exploited to deliver the photocurrents with no significant signal loss to the following inverter cascode transimpedance amplifier, hence resulting in an extended dynamic range. The optically measured results of the C-OER with an 850 nm laser source demonstrate large output pulses. The C-OER chip consumes 47.8 mW from a 1.8 V supply and the core occupies 0.087 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a 52-to-57 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with a novel I/Q phase tuning technique based on a body bias control method. The QVCO employs an in-phase injection-coupling (IPIC) network comprising four diode-connected FETs for the quadrature phase generation. The I/Q phase error is calibrated by controlling the body bias voltage offset of the QVCO's four core FETs. This technique effectively covers a wide range of I/Q phase error between −13.4° and +10.7°. It also minimally induces the unwanted variations in the phase noise, current dissipation, and oscillation frequency, which were found to be only 0.4 dB, 0.07%, and 36 MHz, respectively. After the IPIC-QVCO, a phase-tunable two-stage LO buffer employing a 3-bit switched-capacitor bank was added for additional phase tuning, leading to the extension of the phase tuning range up to −22.7–+20.0°. The proposed QVCO is implemented in a 40 nm RF CMOS process. The measured results show that the QVCO covers a frequency band from 52.4 to 57.6 GHz while consuming 26.2 mW. The phase noise and the figure-of-merit of the QVCO are −91.8 dBc/Hz at 1 MHz offset and −172.4 dBc/Hz, respectively. We also realized a fully integrated 55 GHz quadrature RF transmitter employing the phase-tunable QVCO and LO generator. The effectiveness of the proposed phase-tunable LO generator was confirmed by verifying the image rejection ratio (IRR) calibration at the RF output. [ABSTRACT FROM AUTHOR]

This paper presents a low-noise inverter-based current-mode instrumentation amplifier with tunable gain and bandwidth for electromyogram (EMG) and electrooculogram (EOG) biopotential signals, targeting low input noise while maintaining low power consumption. The gain tuning method is based on pseudo-resistors, whereas the bandwidth is tunable due to a varactor system that is controlled by the same control voltage that tunes the gain. The circuit was designed and manufactured using the 110 nm UMC CMOS technology node, occupying an area of 0.624 mm2. The circuit presents a functioning mode for each biopotential signal with different characteristics, for the EMG a gain of 34.7 dB and a bandwidth of 1412 Hz was measured, with an input referred noise of 1.407 μV which matches a noise efficiency factor of 1.44. The EOG mode achieves a 39.5 dB gain and a 22.4 Hz bandwidth while presenting an input-referred noise of 0.829 μV corresponding to a noise efficiency factor of 6.37. For both modes, the supply voltage is 1.2 V and the circuit consumes 1 μA. [ABSTRACT FROM AUTHOR]

In this paper, a low-voltage low-dropout analog regulator (ALDO) based on a native n-channel MOS transistor is proposed. Application of the native transistor with the threshold voltage close to zero allows elimination of the charge pump in low-voltage regulators using the pass element in a common drain configuration. Such a native pass transistor configuration allows simplification of regulator design and improved performance, with supply voltages below 1 V, compared to commonly used regulators with p-channel MOS transistors. In the presented design of ALDO regulator in 180 nm CMOS X-FAB technology, an output voltage of 0.7 V was achieved with an output current of 10 mA and a supply voltage of 0.8 V. Simulation results show that despite the low supply voltage, output voltage spikes do not exceed 70 mV at the worst technology corner when output current transients from 100 µA to 10 mA. Under such conditions, stable operation and power supply rejection PSR = 35 dB were achieved with an output capacitance of 0–500 pF. The proposed regulator allows to push the limit of ALDO regulator applications to voltages below 1 V with only slight degradation of its performance. [ABSTRACT FROM AUTHOR]

This paper proposes a small-size broadband triangular monopole chip antenna for millimeter wave band applications. Process using 0.18 μm CMOS process and antenna design using Met-al_6. Triangular patch design and feed line length analysis to achieve a better reflection coefficient and also dig three circular slots at the grounding point to achieve better impedance matching. The operating frequency of the chip antenna is 62–100 GHz below the reflection coefficient −10 dB standard, with a fractional bandwidth of 54%. The maximum gain is −0.4 dBi at 64 GHz. The efficiency is 40.9%. The overall chip size is 1.2 × 1.2 (mm2). After measurement and verification, the proposed antenna reflection coefficient is similar to the simulation trend and has better resonance. The chip antenna frequency range proposed in this article covers the 5G NR FR2 frequency band. The proposed chip antenna can be applied in related fields such as the Internet of Things, Industry 4.0, and biomedical electronics. [ABSTRACT FROM AUTHOR]

In this paper, an optimized memristor emulator circuit is designed, by using nine MOSFET transistors and a ground capacitor. Our area- and power-optimized emulator circuit can be used for basic data storage and processing at the monitoring edge, in real-time applications. The memristor shows a nonlinear voltage–current relationship, but no multiplier circuit provides the memristor's nonlinear characteristics. As a result, the proposed memristor emulator has a very low chip area. The memristor circuit is designed in LTSpice, using 16 nm and 45 nm CMOS technology parameters, and the operating voltage is ±0.9 V. In this research, the theoretical derivations are validated using the simulated results of the memristor emulator circuit using different frequencies, capacitors, and input voltages in SPICE simulations. [ABSTRACT FROM AUTHOR]

Multiband terahertz (THz) detectors show great application potential in imaging, spectroscopy, and sensing fields. Thermal detectors have become a promising choice because they could sense THz radiations on the whole spectrum. This paper demonstrates the operation principle, module designs with in-depth theoretical analysis, and experimental validation of a room-temperature CMOS monolithic resonant triple-band THz thermal detector. The detector, which consists of a compact triple-band octagonal ring antenna and a sensitive proportional to absolute temperature (PTAT) sensor, has virtues of room-temperature operation, low cost, easy integration, and mass production. Good experimental results are obtained at 0.91 THz, 2.58 THz, and 4.2 THz with maximum responsivities of 32.6 V/W, 43.2 V/W, and 40 V/W, respectively, as well as NEPs of 1.28 μW/Hz0.5, 2.19 μW/Hz0.5, and 2.37 μW/Hz0.5, respectively, providing great potential for multiband THz sensing and imaging systems. [ABSTRACT FROM AUTHOR]

This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design's robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network. [ABSTRACT FROM AUTHOR]

This paper presents a compact balun with a common inductor design. The design used Wilkinson-type balun topology with modified lumped transmission lines and a common inductor to realize circuit size reduction on a lossy CMOS process. Measurements of the prototype chip had a reflection coefficient below 17.8 dB at all ports, an insertion loss of 1.98 dB, and an isolation of 16.8 dB. The chip size was only 0.025λ0 × 0.034λ0. [ABSTRACT FROM AUTHOR]

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it. [ABSTRACT FROM AUTHOR]

This paper presents a multi-band ultra-low power (ULP) receiver with N-Path Switched-Capacitor (NPSC) networks in 90 nm CMOS process. The NPSC is integrated into the feedback loop of the low noise amplifier (LNA) to flexibly provide narrowband input matching at multiple sub-GHz Industrial, Scientific, and Medical (ISM) bands by adjusting the switching frequency. Moreover, the LNA with an NPSC network is utilized to suppress the out-of-band signal at the input and output of the LNA, simultaneously. In order to achieve an ultra-low power consumption, a sub-threshold LNA and four passive NPSC mixers are implemented in this receiver. The ULP receiver achieves a measured gain of 40 ± 2 dB in ISM bands (430/860/915/960 MHz). The measured noise figure and out-of-band IIP3 are 10 ± 0.5 dB and − 0.3 ± 2 dBm, respectively. The ULP receiver chip consumes 320 μ W at 0.4 V power supply and occupies a chip area of 0.31 mm 2 . [ABSTRACT FROM AUTHOR]

Flat-field correction (FFC) is commonly used in image signal processing (ISP) to improve the uniformity of image sensor pixels. Image sensor nonuniformity and lens system characteristics have been known to be temperature-dependent. Some machine vision applications, such as visual odometry and single-pixel airborne object tracking, are extremely sensitive to pixel-to-pixel sensitivity variations. Numerous cameras, especially in the fields of infrared imaging and staring cameras, use multiple calibration images to correct for nonuniformities. This paper characterizes the temperature and analog gain dependence of the dark signal nonuniformity (DSNU) and photoresponse nonuniformity (PRNU) of two contemporary global shutter CMOS image sensors for machine vision applications. An optimized hardware architecture is proposed to compensate for nonuniformities, with optional parametric lens shading correction (LSC). Three different performance configurations are outlined for different application areas, costs, and power requirements. For most commercial applications, the correction of LSC suffices. For both DSNU and PRNU, compensation with one or multiple calibration images, captured at different gain and temperature settings are considered. For more demanding applications, the effectiveness, external memory bandwidth, power consumption, implementation, and calibration complexity, as well as the camera manufacturability of different nonuniformity correction approaches were compared. [ABSTRACT FROM AUTHOR]

This paper presents an integrated circuit for time-based electrical impedance spectroscopy (EIS) of sensors. The circuit exploits maximum-length sequences (MLS) in order to perform a broadband excitation of the sensors under test. Therefore, the measured time-domain EIS is obtained by cross-correlating the input with the output of the analog front end (AFE). Unlike the conventional digital approach, the cross-correlation operation is performed in the analog domain. This leads to a lower RMS error in the measured time-domain EIS since the signal processing is not affected by the quantization noise of the analog-to-digital converter (ADC). It also relaxes the sampling frequency of the ADC leading, along with the lack of random access memory (RAM) usage, to a reduced circuit complexity. Theoretical concepts about the circuit's design and operation are presented, with an emphasis on the thermal noise phenomenon. The simulated performances are shown by testing a sensor's equivalent model composed of a 50 kΩ resistor in parallel with a 100 p F capacitor. A time-based EIS output of 255 points was obtained with a maximum tested frequency of 500 k Hz and a simulated RMS error of 0.0177% (or 177 ppm). [ABSTRACT FROM AUTHOR]