Search

We demonstrate the frequency synchronization of multiple single-flux quantum (SFQ) oscillators with different oscillation frequencies. To synchronize these SFQ oscillators, a common constant bias current is supplied to the SFQ oscillators without any bias resistors. When an SFQ oscillator oscillates at a frequency of f, the average voltage across the Josephson junction comprising the SFQ oscillator is f Φ 0 , where Φ 0 is the flux quantum in the superconductor. The bias currents supplied to the SFQ oscillators are redistributed to eliminate the average voltage difference output from the SFQ oscillators. As a result, the oscillation frequencies of all the SFQ oscillators are synchronized. Simulation results indicate that SFQ oscillators with an oscillation frequency difference of more than 50 GHz can be synchronized. We experimentally demonstrate the frequency synchronization of two SFQ oscillators composed of circular Josephson transmission lines. Frequency synchronization is expected to contribute toward the development of a low-power stable clock source stabilizing SFQ circuit operation.

CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

Proposed to apply the virtual instrument way to structure the noise generator, according to the complex features of the noises on the low-voltage power line. It talks about the design of the core circuit. used the CPLD-based DDS to stimulate the PLL frequency synthesiser to form the clock generator. Analyzed the method to suppress the phase-noise and the spurious signals of the frequency-synthesis system, proposed to use the balanced scrambling system to suppress the spurious noises from the phase truncation, solved the difficulties in the broad-band signal coupling.

Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm−2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters βc of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.

In this paper, a novel hybrid digital-controlled oscillator (DCO) is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consists of two parts: DCO_high and DCO_low. The DCO_high decides the coarse output frequency of DCO, and adopts the cascade structure to decrease the area. The DCO_low adopts the chain structure with three-state buffer, and decides the fine output frequency of DCO. Compared with traditional cascade DCO, the proposed hybrid DCO features higher precision with less inherent delay. Therefore the clock generator can tolerate process, voltage and temperature (PVT) variation and meet the needs of different conditions. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm 2 chip area. The output frequency is adjusted from 15-120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6-1.8 V supply voltage and 0-80 ℃ temperature variations in TT, FF, SS corners.

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator (PCG) at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process corner and the driver transistor's width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator (PCG). The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder (RCA) and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.

Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 × 256 pixels organized in a square pixel-array with 55 μm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

This paper presents a 10-bit 80-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) suitable for integration in a system on a chip (SoC). By using the top-plate-sample switching scheme and a split capacitive array structure, the total capacitance is dramatically reduced which leads to low power and high speed. Since the split structure makes the capacitive array highly sensitive to parasitic capacitance, a three-row layout method is applied to the layout design. To overcome the charge leakage in the nanometer process, a special input stage is proposed in the comparator. As 80 MS/s sampling rate for a 10-bit SAR ADC results in around 1 GHz logic control clock, and a tunable clock generator is implemented. The prototype was fabricated in 65 nm 1P9M (one-poly-nine-metal) GP (general purpose) CMOS technology. Measurement results show a peak signal-to-noise and distortion ratio (SINAD) of 48.3 dB and 1.6 mW total power consumption with a figure of merit (FOM) of 94.8 fJ/conversion-step.

A novel bioelectrical impedance spectroscopy system based on the digital auto-balancing bridge method improved from the conventional analogue auto-balancing method is presented for bioelectrical impedance measurements. The hardware of the proposed system consists of a reference source, a null detector, a variable source, a field programmable gate array, a clock generator, a flash and a USB controller. Software implemented in the field programmable gate array includes three major blocks: clock management, peripheral control and digital signal processing. The principle and realization of the least-mean-squares-based digital auto-balancing algorithm is introduced in detail. The performances of our system were examined by comparing with a commercial impedance analyzer. The results reveal that the proposed system has high speed (less than 3.5 ms per measurement) and high accuracy in the frequency range of 1 kHz-10 MHz. Compared with the commercial instrument based on the traditional analogue auto-balancing method, our system shows advantages in measurement speed, compactness and flexibility, making it suitable for various bioelectrical impedance measurement applications.

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop (DLL), and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 μm 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.

This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is com- patible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under 4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 W with a sensitivity of -9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 m CMOS technology and the chip size is 880 880 m 2 .

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions, respectively. The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable. In order to further improve the accuracy of phase alignment and phase shift, a VCO design based on a novel quick start-up technique is proposed. A new delay partition method is also adopted to improve the speed of the post-scale counter, which is used to realize the programmable phase shift and duty cycle. A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz. The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps, respectively. The settling time is approximately 2 μs.

A novel monolithic digitalized random carrier frequency modulation spread-spectrum clock generator (RCF-SSCG) is proposed. In this design, the output frequency of the proposed RCF-SSCG changes with the intensity of the capacitive charge and discharge current. Its analytical model is induced and the effect of the modulation parameters on the spread spectrum is numerically simulated and discussed. Compared with other works, this design has the advantages of small size, low power consumption and good robustness. The circuit has been fabricated in a 0.5 μm CMOS process and applied to a class D amplifier in which the proposed RCF-SSCG occupies an area of 0.112 mm2 and consumes 9 mW. The experimental results confirm the theoretical analyses.

A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and offset cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm2.

We evaluate the performance of a single flux quantum (SFQ) circuit and discuss its possible system-level application. First, we describe an optical-electrical-SFQ hybrid router system that is divided into three functions: an SFQ packet-routing function, a control function, and an optical transmission function. For the packet-switching core, we have developed a packet-switching architecture based on an internal speedup time-shifted Batcher Banyan approach. Our simulated results show that this architecture should provide good scalability and a low packet-loss rate. Additionally, we have fabricated an asynchronous pulse arbitration circuit. This circuit is a key component in our packet-switching system. The circuit synchronizes two asynchronous incoming signals without any global clock signals. It consists of a clock generator based on a ring oscillator and data latches. By measuring the average output voltage of the Josephson junction, we confirmed the output signal control by the clock at over 60 Gbps throughput.