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This study examined the effects of hydrogen incorporation in amorphous indium gallium zinc oxide (IGZO) on the performance and photo-bias stability of the resulting thin-film transistors (TFTs). It was found that the threshold voltage of IGZO TFTs was negatively shifted without significant loss of the field-effect mobility and ION/OFF ratio with increasing hydrogen concentration, suggesting that interstitial hydrogen can act as a shallow donor. The hydrogen-doped device, however, showed more negative bias illumination stress (NBIS) instability than the undoped device, which cannot be explained by the simple shallow donor model. This NBIS-induced degradation might be associated with the increased tailing state distribution, which may stem from a hydrogen-related complex defect or compensation.

We have investigated the stability of short-channel (1.5 µm) p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs) under AC bias stress. The threshold voltage of the short-channel (L=1.5 µm) poly-Si TFT was increased by about -7.44 V after AC bias stress, whereas the threshold voltage of the long-channel poly-Si TFT was relatively stable. A two-step degradation process was also observed. In the first step, the threshold voltage of short-channel poly-Si TFTs underwent a consistent positive shift for 100 s. In contrast, the threshold voltage started to undergo a negative shift when accompanied by significant degradation in the subthreshold region. This negative shift of threshold voltage and the significantly degraded subthreshold swing value in the short-channel TFT under dynamic stress may be mainly due to the generation of stress-induced deep- and shallow-level trapping states near the drain junction.

We have investigated the reliability of short-channel (L = 1.5 µm) p-type excimer-laser-annealed (ELA) polycrystalline silicon (poly-Si) TFTs under hot-carrier related static bias stress. The threshold voltage (ΔV TH = 0.59 V) of short-channel TFTs (L = 1.5 µm) was significantly more shifted to the positive direction than that (ΔV TH = 0.02 V) of long-channel TFTs (L = 7 µm) under the same stress condition for 100 s. This positive shift of threshold voltage may be attributed to electron trapping at the interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the normal and drain-source swapped modes as well as the capacitance–voltage (C–V) characteristics with variation in channel length after the bias stress indicate that the electron trapping at the gate insulator/channel interface mainly occurred near the drain junction region. Furthermore, the threshold voltage of the short-channel ELA poly-Si TFTs with L = 1.5 µm was largely increased as the stress temperature was increased from room temperature to 100 °C, which indicates that the impact ionization occurs more at higher temperature.

We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔV TH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔV TH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (C GD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage V FB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

In this study, we analyzed the temperature-dependent characteristics of amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs). We observed that a-IGZO TFTs obey the Meyer–Neldel rule (MN rule) at low gate-to-source voltage (V GS) and the inverse MN rule at high V GS, both of which can be explained by the statistical shift of Fermi level and electrostatic potential. Large Fermi level movement for small V GS change and the inverse MN rule, which are hardly observed for conventional amorphous TFTs, indicate that there is a very low density of state (DOS) in the sub-bandgap region for a-IGZO TFTs and the performance of TFTs is not affected by contact characteristics, respectively. By using the field-effect method and considering surface band bending, we extracted the DOS in the sub-bandgap region, the distribution of which is clearly distinguished by deep and tail states. The calculated parameters for tail and deep states were N ta = 3.5 ×1017 cm-3 eV-1, E ta = 0.18 eV, N da = 1.6×1016 cm-3 eV-1, and σda = 0.21 eV.

A high-performance p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated on a glass substrate. We have investigated the electrical characteristics of short-channel p-type ELA poly-Si TFTs under off-state bias stress. We have found that the threshold voltage of the short-channel TFT (L = 1.5 µm) significantly shifted in the positive direction under off-state bias stress (ΔVTH = 2.71 V), whereas the threshold voltage of long-channel TFT (L = 7 µm) barely moved in the positive direction (ΔVTH = 0.11 V). This positive shift of threshold voltage in the short-channel TFT may be attributed to electron trapping at an interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the forward and reverse modes after the off-state bias stress indicate that the electron trapping at the gate insulator/channel interface occurred near the drain junction region. The leakage current of the ELA poly-Si TFT was also suppressed without reducing the on-current level under the off-state bias stress due to the creation of a pseudo-LDD region.

The use of a double-layer, plasma-enhanced chemical vapor deposited SiO2/SiN x film as a gate dielectric material for polysilicon thin-film transistors was investigated in order to reduce mobile ion contamination and to improve gate oxide integrity degradation. We observed that the interposed silicon nitride film between the gate electrode and the SiO2 gate insulator prevents the incorporation of mobile ions into the SiO2 film, and also increases the breakdown voltage of the gate-insulating film. The mobile ion densities for the double SiO2/SiN x and single SiO2 gate dielectrics (no interposed SiN x layer between the gate electrode and SiO2 gate insulator) were 1.3 ×1011 and 1.7 ×1012/cm2, respectively. The breakdown fields at the 50% failure points in the Weibull plots for the double and single dielectric cases were 8 and 5 MV/cm, respectively. We conclude that the silicon nitride layer of the double gate insulator film minimizes ion contamination, leading to the enhancement of breakdown characteristics.