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The super junction (SJ) has been recognized as the " milestone” of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer (VSL). The basic structure of the SJ is a typical junction-type VSL (J-VSL) with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL (R-VSL) with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the J-VSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional " silicon limit” relationship of Ron∝VB2.5, showing a quasi-linear relationship of Ron∝VB1.03.

A novel silicon controlled rectifier (SCR) with high holding voltage ( for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high by adding a long N+ layer (LN+) and a long P+ layer (LP+), which divide the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current (, the two SCRs are turned on at the same time to induce the first snapback with high (. As the increases, the SCR2 will be turned off because of its low current gain. Therefore, the will flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high (. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line Pulse-like) simulation. An optimized of 7.4 V with a maximum failure current ( of 14.7 mA/ is obtained by the simulation.

A lateral current regulator diode (CRD) with field plates is proposed and experimentally demonstrated. The proposed CRD is based on the junction field-effect transistor (JFET) structure. A cathode field plate is adopted to alleviate the channel-length modulation effect and to improve the saturated I—V characteristics. An anode field plate is induced to achieve a high breakdown voltage VB of the CRD. The influence of the key device parameters on the I—V characteristics of the lateral CRD are discussed. Experimental results show that the proposed CRD presents good I—V characteristics with a high VB about 180 V and a low knee voltage (Vk) below 3 V. Furthermore, the proposed CRD has a negative temperature coefficient. The well characteristic of the proposed CRD makes it a cost-effective solution for light-emitting-diode lighting.

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

In this paper, a novel substrate termination technology (STT) for lateral double-diffused MOSFET (LDMOS) based on curved junction extension is proposed and experimentally demonstrated. A low-doped P-substrate, which is inserted in the curved region of the LDMOS, adjusts the high-doped abrupt P-body/N-drift junction with small curvature radius to low-doped P-sub/N-drift junction with large curvature radius, thus reducing peak electric field and avoiding premature avalanche breakdown at the curved abrupt P-body/N-drift junction. The proposed STT has been applied to a super junction (SJ) LDMOS. The experimental results show that the SJ LDMOS with the proposed STT exhibits off-state breakdown voltage (BV) of 800 V, which is the highest BV for the reported SJ LDMOS by far.

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage (BV) for an ultra-high-voltage (UHV) high-side thin layer silicon-on-insulator (SOI) p-channel lateral double-diffused metal-oxide semiconductor (LDMOS). Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state (on-state) BV of the SOI p-channel LDMOS can reach 741 (620) V in the 3-μm-thick buried oxide layer, 50-μm-length drift region, and at −400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.