Search

Phase change memory (PCM) device using a diode as selector exhibits a high level of integration based on 40 nm process, but it still has some reliability problems, such as read disturbance and writing performance. In this paper, we test and improve the read/write reliability of one diode and one resistor (1D1R) structure cell in array with cell size of 12F2 (0.16 μm × 0.12 μm). The 1D1R device has good performance with ultra-high speed (20 ns) and low programming voltage (3.3 V). The cell programmed by current pulse has a better performance than that of voltage operation in amorphous state with respect to read disturb immunity. The ratio of reset/set resistance can be improved by choosing appropriate parameter of write operation. In addition, the endurance characteristics of the devices are investigated. The optimization in read/write operation guarantee that 1D1R device can satisfy the requirements for the high-speed and high-density applications. [ABSTRACT FROM AUTHOR]

Multilevel-cell (MLC) phase change memory (PCM) usually evaluated in the program method, delay or write energy while the endurance characteristic has not been focused on. In this paper, we exploit a staircase-up program and verify method in the current-driven 4 Mb PCM chip to achieve MLC storage. The direct results of the change in the R–I characteristic and resistance distribution during the cycles are displayed. According to the measurement, the PCM device shows four separable resistance levels after 106 operation cycles with a decreasing resistance of full-crystalline state. And the resistance drift and read disturb which affect the cell reliability also are briefly tested. The MLC device shows a good performance where four resistance levels can be separated well after 1000 s and the read endurance under 0.3 V is retained up to 109 cycles. [ABSTRACT FROM AUTHOR]