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The complex dielectric function ([Formula: see text]) of WSe2 monolayer grown by atomic layer deposition is investigated using spectroscopic ellipsometry. Band structure parameters are obtained by standard line-shape analysis of the second-energy-derivative of [Formula: see text] spectra. The fundamental band gap is observed at 2.26 eV, corresponds to transition between valence band (VB) maximum at the K point and conduction band (CB) minimum at Q point in the Brillouin zone (BZ). Two strong so-called A and B excitonic peaks in [Formula: see text] spectra originate from vertical transitions from spin-orbit split (0.43 eV) VB to CB at K point of the BZ. Binding energies of A and B exactions are 0.71 and 0.28 eV, respectively. Well resolved five excited excitons states has been detected within the spectral region between A and B. Energy profile of the Rydberg series shows significant deviation from the hydrogenic behavior, discussed in connection with the 2D hydrogen model. Results presented here will improve our understanding about the optical response of 2D materials and will help to design better optoelectronic applications and validate theoretical considerations.

We investigate the effects of the number of gate fingers (N) and gate width (W) on the high-frequency characteristics of 0.1 µm depletion-mode metamorphic high-electron-mobility transistors (MHEMTs). The extracted gate-to-source capacitance (Cgs), gate-to-drain capacitance (Cgd), intrinsic transconductance (gm,int), and drain conductance (Gds) are proportional to total gate width (wt), whereas intrinsic resistance (Ri) and source resistance (Rs) are inversely proportional to wt. Gate resistance (Rg) linearly increases at various slopes with non-zero gate resistances at zero gate width depending on N. The cutoff frequency ( fT) and maximum frequency of oscillation ( fmax) are calculated using a small-signal model and curve-fitting equations extracted from each small-signal parameter. fT is almost constant; however, fmax is a strong function of Rg1/2 and is affected by both N and wt. A large wt produces a low fmax; however, at a given wt, increasing the number of gate fingers is more efficient than increasing single gate width for maximizing the fmax.

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were fabricated on a flexible stainless-steel (SS) substrate. The stability of the a-Si:H TFT is a key issue for active matrix organic light-emitting diodes (AMOLEDs). The drain current decreases because of the threshold voltage shift (ΔVTH) during OLED driving. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and the gate electrode without additional circuits. The negative voltage biased at the SS substrate can recover ΔVTH and reduced drain current of the driving TFT. The VTH of the TFT increased by 2.3 V under a gate bias of +15 V and a drain bias of +15 V at 65 °C applied for 3,500 s. The VTH decreased by -2.3 V and the drain current recovered 97% of its initial value under a substrate bias of -23 V at 65 °C applied for 3,500 s.

We report a high conversion gain millimeter-wave monolithic IC (MMIC) quadruple subharmonic mixer adopting a novel cascode harmonic generator for an improved conversion gain. The proposed cascode harmonic generator produces 2.9 dB higher fourth harmonic output powers on the average compared with those of the conventional multiplier. The fabricated mixer shows a high conversion gain of 3.4 dB at a local oscillator (LO) power of 13 dBm. High isolations were obtained the LO-to-intermediate frequency (IF) of -53.6 dB and the LO-to-radio frequency (RF) of -46.2 dB, at a frequency of 14.5 GHz. The conversion gain achieved in this work is the best performance among the millimeter-wave MMIC subharmonic mixers reported to date.

We proposed the hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with current-scaling function which is suitable for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current-mirror circuit, this circuit with the cascaded storage capacitors can provide a high data-to-organic light-emitting device (OLED) current ratio without increasing the a-Si:H TFT size. Moreover, since the number of signal line is reduced in the proposed pixel electrode circuit, the pixel electrode layout and the driving scheme can be simplified in comparison to previously reported cascade capacitor circuit. Finally, the proposed circuit can compensate for the threshold voltage variation of the driving TFT as well as the device geometric size mismatch and temperature effect. [DOI: 10.1143/JJAP.46.1343]

To integrate solution-processible organic semiconductors in the array of thin-film transistors, fine-patterned organic thin-film transistors were fabricated by photolithography. Gold, which has a high work function, was used as a source–drain electrode to reduce the energy barrier between the organic semiconductor and the source–drain. Stacked double layers of gold and chromium were deposited and etched on a glass substrate to enhance the poor adhesion of gold on glass, and then a self-assembled monolayer was formed on them. Solutions of an organic semiconductor and a low-k organic gate insulator were spun by a spin coater and patterned by dry etching using a gate metal as a mask. The devices fabricated by this method show good electrical properties, average field effect mobilities of 0.2–0.3 cm2 V-1 s-1, and an on/off current ratio of over 105 in device dimensions of W/L=84/6 µm. The leakage current through the gate insulator between the gate and the source–drain was similar to that of SiNx in amorphous silicon thin-film transistor (a-Si TFT), which is lower than 10 pA. When the bias-stress stability of organic thin film transistors (OTFTs) was compared with that of a-Si TFT, the threshold voltage shift of OTFT was comparable to that of a-Si TFT, which is smaller than 1 V. However, the stability of OTFT should be further improved and discussed.

Since 2001, LS cable Ltd. has been developing the design, manufacturing and evaluation technologies for high temperature superconducting (HTS) power cable system as a member of DAPAS (Dream for Advanced Power system by Applied Superconductivity technology) program in Korea. The 30 m HTS cable system that is rated at 22.9 kV and 1.2 kA giving a rated capacity of 50 MVA had been developed and tested. The cable was designed as a cold dielectric type employing Bi-2223 HTS tapes and polypropylene (PP) laminated paper as the conductor and electrical insulation, respectively. The cable is cooled with sub-cooled liquid nitrogen at temperature from 75 to 77 K. The manufacturing and the installation of the cable system were completed in 2004. Long-term performance test of the cable system has been conducted for six months to verify its electric and mechanical properties in 2005.

We have proposed and successfully fabricated a new serial current mirror pixel design for an active-matrix organic light-emitting diode which consists of four polycrystalline silicon thin-film transistors (poly-Si TFTs) and one capacitor. The non uniformity of OLED current (IOLED) due to the nature of a poly-Si TFT is considerably suppressed. Our experimental results show that the non uniformity of IOLED due to threshold voltage and mobility variation is around 7% whereas that of IOLED is about 25% in the conventional 2-TFT pixel. When supply voltage decreases from 10 V to 9.5 V, the non uniformity of OLED current is suppressed to 2.2% whereas that of OLED current is 35% in the 2-TFT pixel. The proposed pixel can successfully compensate the variation of the electrical characteristics of the poly-Si TFTs as well as provide uniform OLED current despite the supply voltage drop.

Tetraethylorthosilicate (TEOS)-SiO2 formed by two-step plasma enhanced chemical vapor deposition (PECVD) was investigated as gate insulator for low temperature polycrystalline silicon thin film transistors (TFTs). The TEOS-SiO2 deposited at higher RF power conditions showed better reliability than TEOS-SiO2 deposited at lower RF power. The higher reliability of TEOS-SiO2 at higher RF power conditions was stem from the structural improvement of TEOS-SiO2. But TEOS-SiO2 deposited at higher RF power induced higher plasma damage on the interface so that two-step deposition method was introduced to avoid interface damage that can be measured by TFT characteristics such as s factor and mobility of TFTs. For the two-step deposition of gate insulator, 100 A-thick TEOS-SiO2 with low RF conditions was deposited first. Then TEOS-SiO2 with high RF conditions was deposited about 900 A-thick. The gate insulator with two-step deposited TEOS-SiO2 showed similar electrical reliability with gate insulator that was entirely deposited at high RF power conditions. Besides, the two-step deposited gate insulator showed superior interface characteristics than the gate insulator with high RF power conditions. These results indicate that two-step deposition of gate insulator improves gate insulator reliability without deteriorating interface characteristics between active layer and gate insulator.

We examine the effects of thin-film passivation on the DC, RF and noise characteristics of 0.1-µm-gate-length pseudomorphic high-electron-mobility transistors (PHEMTs) when either conventional Si3N4 or low-dielectric-constant benzo-cyclo-butene (BCB) is used for the passivation layer. A significant shift in pinch-off voltage of ~-0.4 V is observed from the PHEMTs after the Si3N4 passivation, whereas no such variation in DC parameters is observed in the case of BCB passivation. Noise figures of the devices are very stable after the BCB passivation and are only ~60% of those in the case of Si3N4 passivation when measured at 55–62 GHz. Other RF parameters are not significantly affected by the passivation materials at a frequency of 50 GHz. We propose that the degradation in DC and noise characteristics can be due to the high density of surface states in the Si3N4 passivation layers; on the other hand, excellent stability in electrical characteristics in the BCB passivations can attribute to the minimized surface states in the passivation layer.

We successfully fabricated metal-ferroelectric-insulator-semiconductor (MFIS) structures using Bi3.465La0.85Ti3O12 (BLT) ferroelectric thin films and SiO2/Si3N4/SiO2 (ONO) stacked buffer layers for single-transistor-type ferroelectric nonvolatile memory applications. The BLT films were deposited on the prepared Pt/Ti/SiO2/Si and ONO/Si substrates by a sol–gel spin-coating method. The dielectric constant and the leakage current density of the prepared ONO film were measured to be 5.6 and 1.0×10-9 A/cm2 at 3 MV/cm, respectively. We found that the material and electrical properties of the BLT films were effectively modulated by the crystallographic orientation control of the thin films, which were strongly affected by the first annealing process at relatively low temperature. While the fabricated MFIS capacitors using (117)-oriented BLT films showed a charge injection phenomenon in C–V properties at high operating voltage, c-axis-oriented BLT-loaded MFIS capacitors showed a memory window of 0.6 V even at a voltage sweep of ±8 V. We conclude from these results that the c-axis-oriented BLT films formed by the newly proposed fabrication method can be successfully applied to single-transistor-type ferroelectric memory cells.

In this paper, we demonstrate both by simulation and experiment that, by using membrane masks, sub-100 nm patterns can be generated with practical mask to wafer distances (∼10 μm). We discuss the straggling problem and membrane mask preparation, and present ion beam lithography results.

In this study, we analyzed phosphorescence lifetime and its accuracy by growing frost for thermographic phosphor thermometry in a low-temperature environment. Mg4FGeO6:Mn particles were coated on an aluminum plate and excited with a UV-LED to obtain phosphorescence signals. The surface temperature was maintained at −20, −15, −10 °C, and the phosphorescence signal was acquired as the frost grew for 3700 s. The lifetime was calculated and compared with the calibration curve under no-frost conditions. The error of the measured lifetime was within 0.7% of that in the no-frost conditions. A 2D surface temperature profile of the target plate was successfully obtained with the frost formation.

Effects of the drift region doping on the device characteristics in SOI BMFET are investigated by two-dimensional device simulation. The simulation results show that higher blocking capability with RESURF principle, larger current gain in high drain current and improved transient behaviour can be obtained by optimizing the drift region doping concentration. It is found that the SOI BMFET with n-resurf layers exhibits not only the excellent on-state characteristics but also higher breakdown voltage.

We have investigated threshold voltage for each gate length in order to find the optimum value for side gate length and side gate voltage. We find clear on?off stages according to the bias conditions of both gates when side gate voltage is above 2 V and side gate length is above 70 nm. We have obtained the minimum short channel effect for a double-gate metal oxide semiconductor field effect transistor (DG MOSFET). We know that the optimum side gate voltage for each side gate length is about 2 V in the case that the main gate length is 70 nm. The cut-off frequency value is 41.4 GHz at LSG = 70 nm. As a result, the DG MOSFET has excellent electrical characteristics and very high cut-off frequency.

In this study, lifetime-based thermographic phosphor thermometry was developed for 2D temperature measurements in a cryogenic temperature environment. A chamber was set up to provide such an environment with temperatures of 300–110 K and accuracy of ±3.5 K. Mg4FGeO6:Mn was used as a sensor material, which was excited by a pulsed UV LED. A high-speed camera with a frequency of 8000 Hz was used for the phosphor thermometry. Calibration was performed at temperatures ranging from 110 to 290 K. The calibration results clearly show variation in the lifetime at different temperatures, and the calibration error is within 1.7%. This measurement is demonstrated in a 2D temperature measurement of an aluminum plate with a heater for both steady and unsteady heat transfer conditions. The measurement results were compared with thermocouple measurements to validate the method.

This study examined the effect of surface moisture on the calibration lifetime in chemically bonded phosphor paint preparation. Mg4FGeO6:Mn was used as a sensor material, which was excited by a pulsed UV LED. A high-speed camera with a frequency of 8000 Hz was used to conduct phosphor thermometry. Five samples with different degrees of surface moisture were selected during the preparation process, and each sample was calibrated 40 times at room temperature. A conventional post-processing method was used to acquire the phosphorescent lifetime for different samples with a 4 × 4-pixel interrogation window. The measurement error and paint uniformity were also studied. The results showed that there was no obvious phosphorescence boundary between the wet parts and dry parts of phosphor paint. The lifetime increased by about 0.0345% per hour during the preparation process, showing the degree of surface moisture had almost no influence on the lifetime measurement. The lifetime changed only after annealing treatment. There was also no effect on the measurement error and uniformity. These results provide a reference for developing a real-time measurement method using thermographic phosphor thermometry. This study also provides a feasible basis for chemically bonded phosphor thermometry applications in humid and low-temperature environments.

Charge-trap flash (CTF) memory using a zirconium nitride (ZrN)-based memristor switch (MRS) is demonstrated for next-generation nonvolatile memory. This device consists of a metal/MRS/nitride/oxide/silicon (M/MRS/N/O/S) structure so that electrical transport via the ZrN-based MRS layer can be utilized. Compared to previous oxide materials used as conduction paths, the proposed CTF device with a ZrN-based MRS exhibits a faster program/erase switching speed (20 ns/7 ns), along with comparable endurance and retention properties.

The improved resistive switching (RS) performance characteristics of nickel nitride (NiN) films-based crossbar array (CBA) memory resistors-such as reduction in the operating voltages, reset current and current/voltage variations; no initial forming process; and set/reset speeds--are demonstrated using nanopyramid-patterned (NPP) platinum-bottom electrodes. Compared with a conventional CBA sample with flat-bottom electrodes, both the voltage and the current of the set and reset operations are respectively reduced when NPP samples are used. The drastic reduction in the variation of the operating voltage and current is of particular interest. We explain the RS process using the model of the redox-reaction-mediated formation and rupture of the conducting filaments in the NiN films, based on the capacitance-voltage and conductance-voltage characteristics under different resistance states.

We demonstrate highly uniform resistive-switching (RS) characteristics of an SiN nanorod (NR) device fabricated by nanosphere lithography. In the RS experiments, variations in set and reset voltages for the SiN NR device are dramatically reduced to 0.2 V from 0.45 V in conventional SiN thin films. In addition, the resistance ratio (103) between set and reset states is larger and stably maintained without any degradation. As a result, in the resistive random access memory (RRAM) cells with a filament-based RS mechanism, the RS behavior of NR-based RS materials is more uniform than that of the conventional films as a result of reducing the number of conducting paths in the SiN layer.

Various material properties of the perhydropolysilazane spin-on dielectric (PHPS SOD) were examined and analyzed in this study as potential inter-layer dielectrics (ILDs) integrated for Si circuits of 30 nm technology or beyond. The spin-coated PHPS (18.5 wt%) layers converted at 650 °C showed comparable but less perfect thermal conversion to silica than the films converted at 1000 °C, however exhibiting excellent gap filling (15 nm gap opening, aspect ratio (AR) of ~23) and planarization (degree of planarization (DOP) = ~73% for 800 nm initial step height, cusp angle = ~16°) sufficient for the Si integration. PHPS SOD layers cured at 650 °C were integrated ILDs in the 0.18 µm Si front-end-of-the-line process, and the estimated hot-carrier reliability of n-channel metal oxide semiconductor transistors (ten years at a drain voltage of 1.68 V) had no significant difference from that of the transistors integrated with the conventional borophosposilicate glass ILDs. A modified contact pre-cleaning scheme using N2O plasma treatment also produced uniform and stable contact chain resistances from the SOD ILDs.

The authors report a silicon-based one-diode–type resistive-switching memory (RRAM) device with self-rectifying properties and high electrical properties. The RRAM cell consisted of Al/Cr–SrTiO3/Si and revealed intrinsic diode properties, so that unwanted sneaky currents could be removed from an RRAM crossbar array without extra switching devices. The insulator–metal transition property of the proposed device was explained using the space-charge–limited conduction mechanism. The memory device showed good characteristics including high ON/OFF ratio (~106), low reset current (~10-11 A), high speed at low voltage (200 ns, 2 V), and reasonable endurance (>104 cycles) and retention characteristics (>104 s).

We have investigated the stability of short-channel (1.5 µm) p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs) under AC bias stress. The threshold voltage of the short-channel (L=1.5 µm) poly-Si TFT was increased by about -7.44 V after AC bias stress, whereas the threshold voltage of the long-channel poly-Si TFT was relatively stable. A two-step degradation process was also observed. In the first step, the threshold voltage of short-channel poly-Si TFTs underwent a consistent positive shift for 100 s. In contrast, the threshold voltage started to undergo a negative shift when accompanied by significant degradation in the subthreshold region. This negative shift of threshold voltage and the significantly degraded subthreshold swing value in the short-channel TFT under dynamic stress may be mainly due to the generation of stress-induced deep- and shallow-level trapping states near the drain junction.

We have investigated the reliability of short-channel (L = 1.5 µm) p-type excimer-laser-annealed (ELA) polycrystalline silicon (poly-Si) TFTs under hot-carrier related static bias stress. The threshold voltage (ΔV TH = 0.59 V) of short-channel TFTs (L = 1.5 µm) was significantly more shifted to the positive direction than that (ΔV TH = 0.02 V) of long-channel TFTs (L = 7 µm) under the same stress condition for 100 s. This positive shift of threshold voltage may be attributed to electron trapping at the interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the normal and drain-source swapped modes as well as the capacitance–voltage (C–V) characteristics with variation in channel length after the bias stress indicate that the electron trapping at the gate insulator/channel interface mainly occurred near the drain junction region. Furthermore, the threshold voltage of the short-channel ELA poly-Si TFTs with L = 1.5 µm was largely increased as the stress temperature was increased from room temperature to 100 °C, which indicates that the impact ionization occurs more at higher temperature.

The authors present a highly efficient program method for high-speed, low-voltage, and multi-bit/cell operation in the conventional silicon/oxide/nitride/oxide/silicon structure. This method uses a forward bias for collecting the electrons into the substrate whilst both substrate and drain biases are used for injecting the electrons into the nitride layer. With an aid of the substrate bias for electron injection, we obtained a program time as short as 600 ns and an ultralow-voltage operation with a drain voltage of 2 V and a substrate voltage of -3 V. In addition, a localized charge-injection near the junction edge was confirmed with a threshold voltage difference of 1 V between the forward and reverse read.

We examined the thermal stability of a W/TiN/Ti/Si metallization system by changing the thickness ratios of the plasma-treated (PT) to plasma-untreated regions (5 nm × 6/0 nm, 5 nm × 4/10 nm, 5 nm × 3/15 nm, 5 nm × 2/20 nm and 0/30 nm/nm) for the metal-organic-chemical-vapor-deposition (MOCVD) TiN diffusion barriers. From in situ film stress measurements taken during thermal cycles, the best thermal stability was achieved when about half of the thickness at the bottom of the MOCVD-TiN was N2–H2 PT. X-ray photoelectron spectroscopy and cross-sectional transmission electron microscopy revealed that this barrier structure successfully prevented the interdiffusion of the diffusing species from the WSi2 formation at the interface even after thermal annealing at 850 °C for 30 min, and this superior thermal stability was due to the microstructural evolution of the diffusion barrier comprising the amorphous layer for the top half and the oxygen-stuffed crystalline layer at the bottom. From the same plasma-treatment condition, the lowest leakage currents were obtained from both n+ and p+ 10 k array chains of the contacts with a diameter of 350 nm and an aspect ratio of ~1.

We report on the dynamics of bio molecules and a high polymer in a water environment by using imaging ellipsometry (IE). The morphology of collapsed films of arachidic acid (AA) and poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinylene] (MEH-PPV) Langmuir monolayers in a liquid solution is investigated. The IE images clearly show that the multilayer domains and thickness of the collapsed region change sensitively depending on Langmuir compression. Also, the adsorption of bovine serum albumin is observed by using total internal reflection resonance IE (TIRIE), which has the advantage of IE and surface plasmon resonance. We believe that IE is a powerful technique for analysis and applications of bio materials.

We investigated low-temperature SiO x conversion methods for the spin-coated perhydropolysilazane (a diluted dibutyl-ether solution) films prepared on (100) Si substrates under different curing schemes. From the Fourier transform-infrared (FTIR) spectroscopy and refractive index (RI) measurements, conversion to high-density SiO x was observed for the curing methods of dipping the coatings into various aqueous solutions such as H2O2, NH4OH, and deionized water with or without 405-nm ultraviolet irradiation at near room temperature. The SiO x films cured in H2O2 solution at 80 °C for 10 min exhibited a high conversion efficiency for the SiO x network, as observed from FTIR spectra, RI measurement (∼1.46), O/Si stoichiometry (∼1.5), surface smoothness (roughness x films.

This paper reports the direct observation of the threshold voltage shifts with trapped-charge densities as well as the interface-state densities after 104 program/erase (P/E) cycles at each state of the four levels in the drain edge of the silicon–oxide–nitride–oxide–silicon (SONOS) structure. We prepared a SONOS device with a 3.4-nm-thick tunnel oxide, showing 2-bit and 4-level operations at program voltages of 4–6 V, with a 10-year retention and 104 P/E endurance properties. Then, by using charge pumping methods, we observed the vertical and the lateral distributions of the trapped-charges and their interface-states with the gate biases at each level of the four states in the drain edge. The trapped-charges densities at the “10”, “01”, and “00” states in the drain region were estimated to be 1.4×1012, 3.0×1012, and 4.9×1012 cm-2, respectively, with a lateral width of 220 nm. The peak location of the interface-state density was shifted from the drain edge to the channel with an increase in the gate bias. These observations will be quite useful to optimize the program conditions for reliable 4-bit/cell SONOS operations.

In this paper, we present a simple and reliable technique for determining the small-signal equivalent circuit model parameters of the 0.1 µm metamorphic high electron mobility transistors (MHEMTs) in a millimeter-wave frequency range. The initial eight extrinsic parameters of the MHEMT are extracted using two S-parameter (scattering parameter) sets measured under the pinched-off and zero-biased cold field-effect transistor conditions by avoiding the forward gate biasing. Furthermore, highly calibration-sensitive values of the Rs, Ls and Cpd are optimized by using a gradient optimization method to improve the modeling accuracy. The accuracy enhancement of this procedure is successfully verified with an excellent correlation between the measured and calculated S-parameters up to 65 GHz.

An effective resistive-switching effect has been observed in silicon nitride (Si3N4) dielectrics in Ag/Si3N4/Al memory cells. The ratio of the low resistance to high resistance state was larger than 107 at ±1.2 V for a 10 nm thick Si3N4 layer. This switching behavior is attributed to a change in the conductivity of the Si3N4 dielectrics, depending on whether nitride-related traps are filled with electrons under positive biases or unfilled under negative biases. This assertion is experimentally confirmed from the relationship between the amount of charges trapped in the Si3N4 layer and the corresponding changes in its resistance with respect to bias voltages. In addition, the formation or dissolution of the conductive path is confirmed by conductive atomic force microscopy current images.

We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔV TH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔV TH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (C GD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage V FB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

A high-performance p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated on a glass substrate. We have investigated the electrical characteristics of short-channel p-type ELA poly-Si TFTs under off-state bias stress. We have found that the threshold voltage of the short-channel TFT (L = 1.5 µm) significantly shifted in the positive direction under off-state bias stress (ΔVTH = 2.71 V), whereas the threshold voltage of long-channel TFT (L = 7 µm) barely moved in the positive direction (ΔVTH = 0.11 V). This positive shift of threshold voltage in the short-channel TFT may be attributed to electron trapping at an interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the forward and reverse modes after the off-state bias stress indicate that the electron trapping at the gate insulator/channel interface occurred near the drain junction region. The leakage current of the ELA poly-Si TFT was also suppressed without reducing the on-current level under the off-state bias stress due to the creation of a pseudo-LDD region.

A surface tension driven micropump harnessing the pressure difference generated by drops of different curvature radii proves to be a simple and attractive passive method to drive fluid flow in microdevices. Here we observed the appearance of backward flow when the initial sizes of the droplets at the inlet and outlet ports are similar. To explain this phenomenon several hypotheses have been investigated. Consideration of the inertia of the fluid in the channel revealed that it alone is insufficient to explain the observed backward flow. We discovered that rotational flow inside the outlet droplet could be a source of inertia, explaining the generation of the backward flow. In addition, we have experimentally determined that the ratio of the volumes of the initial outlet drop and inlet drop correlates with the occurrence of the backward flow.

We report the effect of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon (MONOS) capacitors. Four samples, namely as-deposited and annealed at 750, 850 and 950 °C for 30 s in nitrogen ambient by a rapid thermal process, were prepared and characterized for comparison. The best performance with the largest memory window of 4.4 V and the fastest program speed of 10 ms was observed for the sample annealed at 850 °C. In addition, the highest traps density of 6.84 × 1018 cm−3 was observed with ideal trap distributions for the same sample by capacitance–voltage (C–V) measurement. These results indicate that the memory traps in the ONO structure can be engineered by post-annealing to improve the electrical properties of the MONOS device.

Indium–tin–oxide (ITO) films doped using an ion implantation system were used as the anode electrode of organic light-emitting diodes (OLEDs). Changes in the characteristics of the doped ITO films were observed and measured in terms of sheet resistance, Hall mobility, contact angle, roughness, transmittance and work function. Boron dopant was used as an impurity to modify the surface of the ITO films. The depth profile of boron concentration was monitored by secondary ion mass spectrometry (SIMS) as a function of dose. Optimum dose was 5×1014 atoms/cm3 at which resistance was lowest. The resistance variation from 16 Ω/sq. of the conventional ITO to 11 Ω/sq. of doped ITO shows that the doped ITO films become more conductive after doping and thermal annealing. The Hall mobility and carrier concentration of boron-doped ITO was 40.4 cm2/Vs and -9.32×1020/cm3 respectively. Contact angle and roughness were investigated by the sessile drop technique and atomic force microscopy (AFM). After doping, the water contact angle of the film surface was changed from 55° to 38° and the root-mean-square roughness of the films was similar to that of conventional ITO. Transmittance in the visible spectrum range was increased from 91% to 96%. Work function was improved from 4.66 eV to 4.86 eV. An OLED device fabricated with a multilayer, boron-doped-ITO/CuPc/NPD/Alq3:C545T/Alq3/LiF/Al, was tested. The device had a luminance of 780 cd/m2 and the lifetime was also increased by approximately 25% compared with those of ITO devices produced under the same conditions.

We examined the effects of gate recess process conditions on the electrical characteristics of 0.1-µm-gate-length metamorphic high-electron-mobility transistors (MHEMTs) by the comparative analysis of small-signal parameters. When the wide-gate-recess method is adopted, significant reductions in gate-to-drain conductance and gate-to-drain capacitance were obtained compared with those obtained by the of narrow-gate-recess method. These differences in small-signal parameters are due to the removal of the entire n+ cap layer and corresponding dissimilarity in gate structure when the wide-gate-recess method is used. The wide-gate-recess method produced ∼1/2 drain-source saturation current and extrinsic transconductance compared with the narrow-gate-recess method. In contract to the DC performances, a markedly enhanced S21 gain of 3.5 dB and an f max of 447 GHz were obtained from the MHEMTs processed by the wide-gate-recess method. This high f max is responsible for the proper selection of the gate recess method for what and is one of the best data thus far reported for 0.1-µm-gate-length MHEMTs.

We present an in situ investigation of As-desorption from the (001) InP surface using surface photoabsorption (SPA). At 470°C, we observed that the SPA signals along [110] remained unchanged even after the AsH3 supply was turned off, while the SPA signal along [110] showed a sharp increase as reported previously. We also measured SPA spectra at several stable states and found that the surface after AsH3 was turned off could not reach that of an In-stabilized surface. We interpret these results in terms of As-desorption occurring possibily as a two-step process, in contrast to P-desorption of a one step process.

We have analyzed the read-out signal obtained from a phase-change optical disc. The marks were recorded both on land tracks and in groove tracks with the focused laser beam of a wavelength of 685nm and a numerical aperture (NA) of 0.6. Characteristics of the read-out signal of marks recorded both on land tracks and in groove tracks were understood by considering the land/groove configuration of the substrate, the reflectance difference and the phase difference between amorphous and crystalline states of a recording layer. By comparing the measured carrier levels obtained from the land and groove tracks with the simulation results based on the diffraction theory, we found that the measured carrier level difference between land and groove recordings resulted mainly from the effects of groove geometry and the phase difference which was estimated to be 20° for our sample disc. For this work, the groove geometry of the substrate and mark sizes were precisely estimated from transmission electron microscopy (TEM) micrographs.

We present an in situ surface photoabsorption (SPA) study on surface structures of (001) InP surfaces. Conventional subtraction spectra of SPA on (001) InP showed two peaks at 430 nm and 600 nm, which we assigned as P dimer and In dimer peaks, respectively. By modifying the conventional subtraction equation to separate contributions from In- and P-stabilized surfaces, we could observe another structure at 400 nm which we interpret as related to In-stabilized surface, showing possibility of complementary role of this modified equation. We also observed evolution of surface states from P- to In-stabilized surfaces at 600°C by the change of PH3 partial pressure.

The paper presents a novel modification of a direct bonding technology. A presented innovation is aimed at fabricating void free interfaces with a low defect density. For this purpose the bonding boundaries are manufactured as grooved, and the bonding annealing is performed under vacuum conditions. It has been found that the grooves act as dislocation traps. A trapped gas escapes through the grooves which facilitates the void removal. By X-ray and electron diffraction techniques the grooves have been observed to flatten rapidly. The electrical properties of the grooved interfaces are as good as those of diffusion p-n junctions.

A hybrid-mode operation of silicon-on-insulator (SOI) bipolar mode field effect transistor (BMFET) is proposed to improve the current gain. The device characteristics are analyzed and verified numerically for hybrid mode, BMFET mode, and double-diffused metal-oxide-semiconductor field effect transistor (DMOS) mode by MEDICI simulation. In hybrid-mode operation, DMOS, lateral bipolar transistor, and BMFET currents flow simultaneously. The proposed SOI BMFET exhibits 30 times larger current gain in hybrid mode operation by connecting DMOS gate to the p+ gate of BMFET structure as compared with the conventional structure without sacrifice of breakdown voltage and leakage current characteristics. The improved current gain characteristics are achieved by the DMOS-gate-induced hybrid effect that lowers the barrier of p-body and reduces the charge in the p-body.