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In this paper, the impact of hot carrier stress on the mismatch properties of n and p metal–oxide–semiconductor (MOS) field-effect transistors (FETs) with different sizes produced using 0.15 µm complementary MOS (CMOS) technology is presented for the first time. The research reveals that hot-carrier injection (HCI) does degrade the matching properties of MOSFETs. The degree of degradation closely depends on the strength of the HC effect. Thus, it is found that, under the stress condition of drain avalanche hot carrier (DAHC), the properties of nMOSFETs rapidly and greatly become worse, but the changes are small for pMOSFETs. For analog circuit parameters, it is found that the after-stress lines of n and pMOSFETs exhibit a cross point in σ (ΔVt,op) drawings. It is suggested that the cross point can be used to indicate the minimal size in order for n and p pairs to have the same degree of ΔVt,op mismatch in designing analog circuits. In addition, interpretations for the differences between n and pMOSFETs and between ΔVt,op and Ids,op mismatches are provided with experimental verifications.

In this study, n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) having 20 and 32 A gate oxide thicknesses of 0.13 µm technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 °C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of Id,op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 °C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the parameter for monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 A, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.

Metal–oxide–semiconductor field-effect transistors (MOSFETs) incorporating hafnium-silicate (HfSiON) dielectrics with different compositions have been fabricated and their hot-carrier injection (HCI) reliability has also been investigated. The experimental results reveal that the HCI degradation of atomic layer deposition (ALD) HfSiON gate dielectrics is minimized at Hf : Si = 1 : 3. Moreover, the experimental results also show that the increment of oxide trapped charges (ΔNot) depends on Hf content and is about one order of magnitude larger than that of interface traps (ΔNit) after channel-hot-carrier (CHC) stress. Finally, some important interfacial parameters, including ΔNit, ΔDit, and ΔNot, have also been characterized through the charge pumping (CP) technique.

Metal–oxide–semiconductor capacitors (MOSCs) and MOS field-effect transistors (MOSFETs) incorporating cerium dioxide (CeO2) dielectrics were fabricated and investigated. In this work, the electrical and interfacial properties were characterized by capacitance–voltage (C–V) and current–voltage (I–V) measurements. The density of interface trap per unit area (Nit), the density of interface trap per unit area and energy (Dit), the energy distribution of interface trap density, and the effective capture cross section (σs) were studied in details. Experimental results showed that the Nit, Dit, and σs were about 3.4×1010 cm-2, 7.3×1010 cm-2 eV-1, and 9.0×10-15 cm2, respectively. In addition, a comparison of interfacial properties among several gate dielectrics was made.