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High-Performance computing (HPC) is rarely accomplished via virtual machines (VMs). In this paper, we present a remake of ivshmem which can change this. Ivshmem was a shared memory (SHM) between virtual machines on the same server, with SHM-access synchronization included, until about 5 years ago when newer versions of Linux and its virtualization library libvirt evolved. We restored that SHM-access synchronization feature because it is indispensable for HPC and made ivshmem runnable with contemporary versions of Linux, libvirt, KVM, QEMU and especially MPICH, which is an implementation of MPI - the standard HPC communication library. Additionally, MPICH was transparently modified by us to get ivshmem included, resulting in a three to ten times performance improvement compared to TCP/IP. Furthermore, we have transparently replaced MPI_PUT, a single-side MPICH communication mechanism, by an own MPI_PUT wrapper. As a result, our ivshmem even surpasses non-virtualized SHM data transfers for block lengths greater than 512 KBytes, showing the benefits of virtualization. All improvements were possible without using SR-IOV.

ASDEX Upgrade is a poloidal divertor experiment very similar to ITER with respect to magnetic field properties and especially to the plasma boundary geometry. A large part of the programme on ASDEX Upgrade is therefore dedicated to investigating and optimizing reactor-relevant plasma boundary issues. This contribution is concerned with H-mode studies and edge physics in general. The L/H-power threshold, H-mode confinement, details of ELM dynamic and 'dithering' L/H-transitions will be discussed. The edge physics investigations are concerned with model calculations and validations, the characteristic 'approach' to the density limit (DL), target plate sputtering and the influence of hydrocarbons, asymmetries and drifts depending on the direction of the toroidal magnetic field, and finally first results of high-Z material experiments.

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness ⩽20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the builtin devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chipʼs edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.