Search

The High Luminosity phase of the Large Hadron Collider will deliver 10 times more integrated luminosity than the existing collider, posing significant challenges for radiation tolerance and event pileup on detectors, especially for forward calorimetry. As part of its upgrade program, the Compact Muon Solenoid collaboration is designing a high-granularity calorimeter (HGCAL) to replace the existing endcap calorimeters. It will feature unprecedented transverse and longitudinal readout and triggering segmentation for both electromagnetic and hadronic sections. The electromagnetic section and a large fraction of the hadronic section will be based on hexagonal silicon sensors of 0.5-1 cm2 cell size, with the remainder of the hadronic section being based on highly-segmented scintillators with silicon photomultiplier readout. The intrinsic high-precision timing capabilities of the silicon sensors will add an extra dimension to event reconstruction, especially in terms of pileup rejection. First hexagonal silicon modules, using the existing Skiroc2 front-end ASIC developed for CALICE, have been tested in beams at Fermilab and CERN in 2016. We present results from these tests, in terms of system stability, calibration with minimum-ionizing particles and resolution (energy, position and timing) for electrons, and the comparisons of these quantities with GEANT4-based simulation. © 2018 CERN for the benefit of the CMS collaboration.. Nuclear Physics Collegio Ghislieri di Pavia China Medical University, Taiwan Institute for Research in Fundamental Sciences aInsitute for High Energy Physics, Beijing, China bLaboratoire Leprince-Ringuet, Palaiseau, France cOrganization for Microelectronics design and Applications (OMEGA), Palaiseau, France dSaha Institute of Nuclear Physics, Kolkata, India eTata Institute for Fundamental Research, Bombay, India fUniversity of Pavia, Pavia, Italy gCERN, Geneva, Switzerland hNational Central University, Chung-Li, Taiwan iNational Taiwan University, Taipei, Taiwan jCukurova University, Adana, Turkey kImperial College of Science, Technology and Medicine, London, U.K. lBoston University, Boston, U.S.A. mCalifornia Insitute of Technology, Pasadena, U.S.A. nCarnegie Mellon University, Pittsburg, U.S.A. oFermi National Accelerator Laboratory, Batavia, U.S.A. pFlorida State University, Tallahassee, U.S.A. qNorthwestern University, Evanston, U.S.A.

International audience; SKIROC2_CMS is a chip derived from CALICE SKIROC2 that provides 64 channels of low noise charge preamplifiers optimized for 50 pF pin diodes and 10 pC dynamic range. They are followed by high gain and low gain 25 ns shapers, a 13-deep 40 MHz analog memory used as a waveform sampler at 40 MHz. and 12-bit ADCs. A fast shaper followed by discriminator and TDC provide timing information to an accuracy of 50 ps, in order to test TOT and TOA techniques at system level and in test-beam. The chip was sent to fabrication in January 2016 in AMS SiGe 0,35 μm and was received in May. It was tested in the lab during the summer and will be mounted on sensors for beam-tests in the fall.

This work has been done in order to study a new technology provided by X-FAB named xt018. It is an SOI (Silicon On Insulator) technology with a minimal gate length of 180 nm. Building blocks have been done to test the advantages and drawbacks of this technology compared to the one currently used (AMS SiGe 0.35 μm). These building blocks have been designed to fit in an existing experience housed by the CALICE collaboration: the read-out chip for the Electromagnetic CALorimeter (ECAL) of the foreseen International Linear Collider (ILC). Performances will be compared to those of the SKIROC2 chip designed by the OMEGA laboratory, trying to fit the same requirements. The chip is being manufactured and will be back for measurements in December, the displayed results are only simulation results and thus the conclusions concerning the performances of these building blocks are subject to change.

Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out.Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement.Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps).Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs.Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer.