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The fabrication methods and characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) stacked complementary metal oxide semiconductor (CMOS) inverters were demonstrated the feasibility for high performance logic circuit applications was verified. The laser crystallization processes were compatible with the poly-Si TFT stacked CMOS inverters and the laser crystallized poly-Si films showed uniform grain size with low surface roughness and excellent crystallinity. In order to fabricate three-dimensional (3-D) stacked poly-Si CMOS inverters, the p-channel MOSTFTs (PMOS) at upper poly-Si layer were stacked on the n-channel MOSTFT (NMOS) at lower poly-Si and interlayer dielectric (ILD) layer. The HfO2 gate dielectrics and Pt metal gates were applied to the upper PMOSTFT to avoid the degradation of lower NMOSTFT. The CMOS inverters fabricated by stacking the poly-Si TFTs revealed good characteristics for the 3-D integrated CMOS applications.

For Si nanocrystals, which are formed by Si ion implantation into a SiO2 layer, the effects of crystal size and interface states on the photoluminescence property are investigated. The Si-implanted SiO2 samples are annealed in an N2 ambience at different temperatures to obtain Si nanocrystals of different sizes. The sample annealed at 1100°C shows a strong and broad photoluminescence (PL) peak at 700 nm (1.77 eV). The observed PL spectrum redshifts when the annealing temperature increases, blue shifts when the samples are oxidized, and redshifts followed by blue shifts when the average size of the Si nanocrystals increases and then decreases with etch depth of the SiO2 layer. Low-temperature annealing in an H2 ambience increases the PL intensity but does not change the PL spectral distribution. Experimental observations indicate that the size of the Si nanocrystal determines the quantum state for carrier excitation and that the interface states at the Si nanocrystal/SiO2 interface provide the nonradiative recombination centers.

Electrical properties of the Silicon quantum dots (Si-QD) light-emitting diodes (LEDs), in its dependence on the nitrogen source used in the silicon nitride (SiN x ) matrix growth, have been studied. Si-QDs are formed in-situ during the SiN x film growth, and no post-annealing process for crystallization was applied. To confirm the electrical properties of the Si-QD devices, we manufacture the Si-QD LED. Both p-type and p+-type Si substrate were tested in role of hole tunneling in the LED performance. The high-resolution transmission electron microscopy (HRTEM) analyses and the current–voltage (I–V) measurement show that the Si-QDs embedded in the SiN x grown with ammonia (NH3) are located at the interface between the SiN x film and the Si substrate. This is related to the observed increase in the forward current by considering a decrease in the hole tunneling barrier width between the Si substrate and the Si-QDs.

In this paper, we demonstrate a novel plasma ion-shower doping (PLAD) technique for fabricating a nanoscale silicon-on-insulator metal-oxide-semiconductor field effect transistors (SOI MOSFETs). The source drain (S/D) extensions of the SOI n-MOSFETs were formed by elevated-temperature (ET) PLAD. Even though activation annealing after PLAD was excluded to minimize the diffusion of dopants, which resulted in laterally abrupt S/D junction, we obtained a low sheet resistance of 920 Ω/□ by the ET PLAD at 230°C. The fabricated SOI n-MOSFET with a gate length of 50 nm adopted in the proposed junction formation technique showed suppressed short-channel effects. The successful operation of a MOSFET with a high-κ gate dielectric and metal gate revealed that the proposed junction formation technique is compatible with devices made of low-thermal-budget material.

This paper presents the electrical characteristics of trigate silicon-on-insulator (SOI) n-type metal–oxide–silicon field-effect transistor (n-MOSFET) devices with a gate length of 50 nm, a channel width of 100 nm, and a channel thickness of 30 nm. The source and drain of these trigate SOI n-MOSFETs were formed by ion-shower doping at 250°C. In particular, activation annealing after ion-shower doping was excluded in order to improve the lateral steepness of the source/drain junction. Without any additional thermal processes, a low sheet resistance (R s) of 1.2 kΩ/□ was obtained by ion-shower doping, and trigate MOSFETs showed satisfactory electrical characteristics. Since the short-channel effect was suppressed and the ratio of maximum drain current to minimum drain current (I max/I min) as ∼105, it is thought that the ion-shower doping process is effective for fabricating short-channel trigate SOI MOSFET devices.

The effects of segregated Ge on the electrical properties of the SiO2/SiGe interface are investigated. It is observed that the segregated Ge near the SiO2/SiGe interface, formed during oxidation of the SiGe layer, affects the threshold voltage of a metal-oxide-semiconductor (MOS) structure, and that the flat-band voltage shift increases when the Ge segregation is increased. The densities of the interface states and fixed charges are measured using the capacitance-voltage (C–V) method, and the relationships between these results and the material properties are examined. From the results, the SiO x structures are responsible for the increased negative fixed charges near the SiO2/SiGe interface. The mechanism proposed for the generation of negative fixed charges is that the oxygen in the Ge pileup region forms a Si–O–Ge bonding structure initially, and then the weaker Ge-O bond can easily be broken, leaving a Si–O– dangling bond and elemental Ge. The Si–O– dangling bond assumes a negative fixed charge state by trapping an electron.

N-channel and p-channel metal-oxide-semiconductor (MOS) thin-film transistors (TFT's) have been fabricated on rapid thermal chemical vapor deposition (RTCVD) polycrystalline silicon-germanium (poly- Si0.88Ge0.12) films by a low temperature (≤550° C) process. These devices employ in-situ n+ doped poly- Si0.65Ge0.35 films as gate electrodes to reduce the process time and temperature, dual-offset spacers to reduce the electric field in the drain junction region, and silicon capping layers to protect the poly-Si1-x Ge x films against oxygen. The I d-V g characteristics in n-channel TFT's, as well as in p-channel TFT's, exhibit good behavior after remote-PECVD hydrogenation. Further improvements on electrical properties in n-channel TFT's are limited by trap-inducing G e behaviors in poly-Si1-x Ge x films.