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This work presents a low cost fluorescence life time measurement system, aimed at carrying out fast diagnostic tests through label detection in a portable system so it can be used in a medical consultation, within a short time span. The system uses Time Correlated Single Photon Counting (TCSPC), measuring the arrival time of individual photons and building a histogram of those times, showing the fluorescence decay of the label which is characteristic of each fluorescent substance. The system is implemented using a Xilinx FPGA which controls the experiment and includes a Time to Digital Converter (TDC) to perform measurements with a resolution in the order of tenths of picoseconds. Also included are a laser diode and the driving electronics to generate short pulses as well as a HV-CMOS implemented Single Photon Avalanche Diode (SPAD) as a high gain sensor. The system is entirely configurable so it can easily be adapted to the target label molecule and measurement needs. The histogram is constructed within the FPGA and can then be read as convenient. Various performance parameters are also shown, as well as experimental measurements of a quantum dot fluorescence decay as a proof of concept.

In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865 mm × 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L = 860 μm/0.2 μm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 μ W per channel.

The need to move forward in the knowledge of the subatomic world has stimulated the development of new particle colliders. However, the objectives of the next generation of colliders sets unprecedented challenges to the detector performance. The purpose of this contribution is to present a bidimensional array based on avalanche photodiodes operated in the Geiger mode to track high energy particles in future linear colliders. The bidimensional array can function in a gated mode to reduce the probability to detect noise counts interfering with real events. Low reverse overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process presents an increased efficiency and avoids sensor blindness by applying the proposed techniques.

This work presents low noise readout circuits for silicon pixel detectors based on Geiger mode avalanche photodiodes. Geiger mode avalanche photodiodes offer a high intrinsic gain as well as an excellent timing accuracy. In addition, they can be compatible with standard CMOS technologies. However, they suffer from a high intrinsic noise, which induces false counts indistinguishable from real events and represents an increase of the readout electronics area to store the false counts. We have developed new front-end electronic circuitry for Geiger mode avalanche photodiodes in a conventional 0.35 μm HV-CMOS technology based on a gated mode of operation that allows low noise operation. The performance of the pixel detector is triggered and synchronized with the particle beam thanks to the gated acquisition. The circuits allow low reverse bias overvoltage operation which also improves the noise figures. Experimental characterization of the fabricated front-end circuit is presented in this work.