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De-embedding is the process of deducing the characteristics of a device under test (DUT) from measurements made at a distance ((Bauer & Penfield, 1974)), often via additional measurements of one or more dummy devices. This article reviews a simple thru-only de-embedding method suitable for on-wafer characterization of 2-port, 4-port, and 2n-port networks having a certain symmetry property. While most conventional de-embedding methods require two or more dummy patterns, the thru-only method requires only one THRU pattern. If the device under measurement is a 2-port and the corresponding THRU pattern has the left/right reflection symmetry, the THRU can be mathematically split into symmetric halves and the scattering matrix for each of them can be determined (Ito & Masu, 2008; Laney, 2003; Nan et al., 2007; Song et al., 2001; Tretiakov et al., 2004a). Once those scattering matrices are available, the effects of pads and leads can be canceled and the characteristics of the device obtained. Themethodwas applied up to 110GHz for characterization of an on-chip transmission line (TL) (Ito & Masu, 2008). In the case of 4-port devices such as differential transmission lines, 4-port THRU patterns with ground-signal-ground-signal-ground (GSGSG) pads or GSSG pads can often be designed to have the even/odd symmetry in addition to the left/right reflection symmetry. In that case, the scattering matrix for a THRU can be transformed into a block-diagonal form representing two independent 2-ports by an even/odd transformation. Then, the 2-port thru-only deembedding method can be applied to the resultant two 2-ports. This 4-port thru-only method was applied to de-embedding of a pair of coupled transmission lines up to 50GHz (Amakawa et al., 2008). The result was found to be approximately consistent with that from the standard open-short method (Koolen et al., 1991), which requires two dummy patterns: OPEN and SHORT. In the above case (Amakawa et al., 2008), the transformation matrix was known a priori because of the nominal symmetry of the THRU. However, if the 4-port THRU does not have the even/odd symmetry or if the device under measurement is a 2n-port with n ≥ 3, the above method cannot be applied. Even if so, the thru-only method can actually be extended to 4-ports without even/odd symmetry or 2n-ports by using the recently proposed S-parameterbased modal decomposition of multiconductor transmission lines (MTLs) (Amakawa et al., 2009). A 2n-port THRU can be regarded as nonuniform multiconductor transmission lines, 2

System-on-a-chip (SoC) has become possible since a great number of circuit elements can be integrated into a single chip by the miniaturization technologies for Si CMOS. Network-onChip (NoC) has been investigated actively, and it is expected to be a new approach for designing the communication subsystems of SoC (Lee et al., 2008). Enormous circuit blocks are loaded onto the NoC, and on-chip networks like local area networks (LANs) in the NoC communicate among these circuit blocks. Since the performance of the NoC is strongly affected by on-chip networks, the construction of efficient on-chip communications infrastructures will be increasingly significant. Some of the important characteristics for on-chip interconnects are bandwidth, latency, and power. In particular, power saving technologies are very important in realizing Green IT (information technology). Power dissipation in on-chip networks mainly occurs at interconnects due to the increase of wiring resistance and capacitance. A significant issue is that power consumption of conventional on-chip interconnects, i.e. so-called RC lines, is proportional to the signal frequency; hence, it is very difficult to reduce energy dissipation per bit. Given the recent trend of high-speed signaling, we have to solve this problem and offer some good solutions. One solution is the use of copper lines and low-k dielectric, and these techniques have been widely applied and reduce power consumption for transmitting signals. However long interconnects still consume large power as in the case of RC lines. Another solution is the introduction of on-chip transmission line interconnects (TLIs). The applications of TLIs have been widely demonstrated. Modulation (Chang et al., 2003), pulsedcurrent-mode (Jose et al., 2006), current-mode-logic (Ito et al., 2004, 2005; Ishii et al., 2006; Gomi et al., 2004), low voltage differential signaling (Ito et al., 2007) and multi-drop (Ito et al., 2008) techniques are proposed, and these techniques enable the improvement of bandwidth, latency and extensibility of on-chip networks. Figure 1 is an image of on-chip networks with TLIs. It is also reported that TLIs have a better power efficiency than the conventional on-chip lines as the line length and signal frequency increase (Ito et al., 2004; Gomi et al., 2004; Ito et al., 2005; Ishii et al., 2006; Ito et al., 2007). Further improvement of the power efficiency at low frequencies is the design challenge in the case of on-chip TLIs. Since current-mode differential amplifiers are usually used for transmitters (Txs) and receivers (Rxs) in TLIs, Tx and Rx consume static power regardless ardless of the signal frequency. This means TLIs waste power if they are applied to paths with a low activity factor or to transmit low bit-rate signals.