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This study presents the design and simulation of a fully differential two-stage op-amp in a 0.18 μm complementary metal-oxide-semiconductor process with a 1.8 V supply voltage. In this op-amp, positive feedback technique and split-length transistors (SLTs) are employed to increase the DC-gain of the op-amp by about 22 dB without affecting the unity-gain bandwidth (UGBW), stability, power dissipation and output voltage swing of the conventional two-stage op-amp. A comprehensive analysis is provided for differential-mode gain, common-mode gain, power supply rejection ratio, input-referred noise, input offset, frequency response and the effect of using SLTs on DC-gain sensitivity. The proposed op-amp is utilised in a flip-around sample-and-hold amplifier (SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%. The post-layout and Monte Carlo simulation results show that the proposed op-amp has better performance than the state-of-the-art designs.

A fully integrated, low power low-noise amplifier (LNA) is implemented for 2.14 GHz band using 65-nm radio frequency CMOS technology. By taking advantage of higher transition frequencies of recent technologies, transistors are biased in the moderate inversion region thus permitting scaling down the supply voltage to 0.7 V. Further, the exploration of design spaces from strong to weak inversions assisted the development of a unified noise factor model. An optimisation is carried out based on the parameter extraction and accordingly an extraction methodology is developed. Overall, the unified model based on the parameter extraction helped in noise estimation in all regions of inversion. The resulting LNA achieves a good power match at the input where the simulated S11 parameter shows an excellent value of −22 dB. Compared to other existing subthreshold cascode LNAs reported in the literature, it shows reasonably better performance in terms of noise and power consumption with a noise figure of 3.74 dB and a moderate power gain of 8.7 dB at a core device current consumption of 450 μA.

To achieve the maximum current rising rate, second-generation Experimental Advanced Superconducting Tokamak (EAST) plasma vertical displacement active feedback power supply applies voltage control mode while retaining the first-generation current tracking mode. When the power supply outputs high voltage, the accompanied frequent over-current protection will return the power to DC side, which leads to over-voltage protection, so the current limiting protection is applied. Experimental results prove that the voltage mode can greatly improve the ability to suppress vertical unstable displacement of plasma.

A low dropout (LDO) voltage regulator operated at 5 V power supply, along with a bandgap reference (BGR) voltage circuit with high power-supply rejection ratio (PSRR) is introduced. In the suggested LDO circuit, a low-pass filter for creating a common gate to transmit supply voltage to the power transistor gate is used. During deployment of the RC filter, an artificial resistor with a value of infinity is utilised, which in addition to reduce the chip occupied area, improves the performance of the low-pass filter at frequencies close to DC, and thus improves the PSRR at these frequencies. In addition, the high PSRR of the circuit is mediated by a low-voltage current mode regulator at the heart of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage ( V reg ) for BGR core and op-amp rather than the V DD . These current mirrors reduce the impact of supply voltage variations. The circuit topology is discussed and simulation results are provided. The LDO is also stable without an output capacitor.

A structure of a dynamic comparator with high-speed low-power and a low-power supply voltage is proposed. The proposed comparator is compared with previous dynamic comparators. For the same size of input/output transistors and latch as well as load capacitance, it is more than 1.3 times faster with

This study describes a 0.38 V digitally controlled low-dropout (LDO) voltage regulator enabling dynamic voltage scaling (DVS) for near/sub-threshold applications. For operating at an ultra-low supply voltage, analogue components are replaced in conventional LDOs with digital counterparts. Especially, a digital reference control that is based on a replica circuit is proposed to improve power supply noise rejection and line regulation of the LDO. The proposed LDO has been designed in a 90 nm regular V T complementary metal oxide semiconductor technology. The LDO can regulate the output voltage from 0.12 to 0.32 V with a supply voltage of 0.38 V. Furthermore, it reaches the current efficiency of 99.3% and the power efficiency of 83.6%, respectively, at a load current of 1 mA. The digitally controllable DVS with 3 mV resolution is achieved.

This study presents a subthreshold complementary metal oxide semiconductor (CMOS) voltage reference circuit that adopts dynamical body bias to compensate the process-related reference voltage fluctuation. The proposed circuit generates a mean reference voltage of 0.781 V at 1.2 V supply and 27°C, reduces the standard deviation (σ) of the reference voltage from 11 mV to only 3 mV, and meanwhile improves the power supply rejection ratio from -30.7 to -51.4 dB. The average temperature coefficient measured from 0 to 100°C is 48 ppm/°C, and the line regulation is 0.34%/V in a supply voltage ranging from 1.2 to 2.3 V. The maximum supply current is 8.1 μA at 1.2 V supply and 100°C, and the chip area is 0.0533 mm 2 in 0.13-μm CMOS technology.

Switch capacitor DC-DC converter is an emerging concept for high dropout application. This paper discusses techniques for output voltage ripple reduction of an embedded dual-switch capacitor - linear regulator-based hybrid DC-DC converter. In spite of deploying the advantage of PSRR property of the linear regulator, the ripple at the output of the convertor is still high. To alleviate this, a new technique of further reduction of the output ripple by introducing synthesised counter ripples through the linear regulator is presented. The conventional and new technique of ripple reduction has been analysed with the help of small signal equivalent circuits. These techniques have been implemented with a hybrid converter for 3.3-V-to-1.35-V conversions. A test chip is fabricated in a 0.18--m standard digital CMOS process to demonstrate the efficacy of the proposed technique. It is found that the trend of ripple reduction by ripple synthesiser in measured results is consistent with the simulation results and also observed in the measured results that the ripple synthesiser reduces the output ripple of a hybrid converter by the factor of 0.52 and 0.45 for the load current of 2.2-mA and 7.3-mA, respectively.

A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth. The OTA is fabricated using the AMI 0.5 m CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB to 10 kHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers very low current consumption of 25 A from a 3.3 V supply. It is suitable for applications such as low drop out voltage regulators.

A frequency compensation technique improving characteristic of power supply rejection ratio (PSRR) for two-stage operational amplifiers is presented. This technique is applicable to most known two-stage amplifier configurations. The detailed small-signal analysis of an exemplary amplifier with the proposed compensation and a comparison to its basic version reveal several benefits of the technique which can be effectively exploited in continuous-time filter designs. This comparison shows the possibility of PSRR bandwidth broadening of more than a decade, significant reduction of chip area, the unity-gain bandwidth and power consumption improvement. These benefits are gained at the cost of a non-monotonic phase characteristic of the open-loop differential voltage gain and limitation of a close-loop voltage gain. A prototype-integrated circuit, fabricated based on 0.35 μm complementary metal-oxide semiconductor technology, was used for the technique verification. Two pairs of amplifiers with the classical Miller compensation and a cascoded input stage were measured and compared to their improved counterparts. The measurement data fully confirm the theoretically predicted advantages of the proposed compensation technique.

A low-dropout regulator (LDO) with high power-supply rejection ratio (PSRR) is presented. The high PSRR at high frequency is enabled by a signal-nulling technique achieved by a wide-bandwidth feedforward path. Experimental results verify the outstanding performance.

Two nanopower CMOS sub-bandgap references have been designed with the Chartered 0.35 mum CMOS process, which generate two precise voltages of 96.6 and 108.9 mV with minimal temperature coefficients of 11.4 and 9.2 ppm/degC, respectively. Both circuits operate properly with a supply voltage down to 1.1 V and a supply current below 26 nA. The power supply rejection ratio for each circuit without any filtering capacitor at 100 Hz and 10 MHz is lower than 60 and 40 dB, respectively.

A 0.9 V fully differential switched-opamp-based sixth-order switched-capacitor bandpass filter, which has frequency response centred at 1.118 kHz with a Q of 0.235 and power saving by a proposed low-power biquad structure, is designed for electroneurography acquisition systems. It is implemented in a 0.18 µm CMOS technology with a normal threshold voltage of 0.48 V. The measured peak signal-to-noise ratio is 52 dB at 1 kHz sinusoid wave with input amplitude of 1 Vpp. In addition, the measured power-supply rejection ratio and common-mode rejection ratio are >40 dB in the desired bandwidth and have peak values of 70 and 67 dB, respectively. A dynamic range of 50 dB for total harmonic distortion of 3% is obtained while dissipating 262 µW and occupying a chip area of 0.35 mm2.

A simple two-stage Miller compensated class AB amplifier is presented which uses single-ended class AB control for accurate setting of the output stage quiescent and minimum currents. This control technique also inherently boosts the amplifier midband positive power supply rejection ratio (PSRR dd ). Measurements show a more than 20 dB improvement in the midband PSRR dd when the amplifier is compared to popular symmetrical class AB amplifiers with similar bandwidth.

A simple circuit technique for improving the midband positive power supply rejection ratio (PSRR dd ) of gain boosted class AB power amplifiers is presented. The technique takes advantage of the bias network and inherent narrow gain boosting amplifier bandwidth and therefore does not require any additional components. Measurements show that more than 20 dB improvement in the midband PSRR dd is obtainable at a frequency of 100 kHz

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.

A fully monolithically-integrated power amplifier with a bandwidth (−3 dB) from 20.5 to 31 GHz was realised in a 0.13 µm standard CMOS technology. A maximum power added efficiency of 13% with a corresponding output power of 13 dBm was achieved at 25.7 GHz with 1.5 V supply voltage.

This article outlines the use of network analysers in measuring voltage quality in low power supply networks. It describes in detail a cooker which was intermittently switching itself on, and how the fault was traced to the rectifier drive of a cable car system some distance away.

An ultra-low supply voltage and low power dissipation fully static frequency InP SHBT divider operating at up to 38 GHz is reported. The fully differential parallel current switched configuration of D-latch maintains the speed advantages of CML circuits while allowing full functionality at a very low supply voltage. The frequency divider operates at up to 38 GHz at a single-ended input power of 0 dBm. The power dissipation of the toggled D-flip–flop is 8 mW at a power supply voltage of 1.3 V. The authors believe this is the lowest supply voltage for static frequency dividers around this frequency in any technology. This low power configuration is suitable for any digital integrated circuit.

A high-linearity and high-efficiency MMIC power amplifier is proposed that adopts a new on-chip adaptive bias circuit, which simultaneously improves efficiency at the low output power level and linearity at the high output power level. The intelligent W-CDMA power amplifier using the adaptive bias circuit extends the maximum linear output power of 0.6 dB and exhibits an improvement of average power usage efficiency of 1.85 times.

A special waveform to replace the power supply of a modified D-latch is presented. The power supply only exists when it is needed. Hence, the amount of switching at certain nodes is reduced. Furthermore, the voltage ramp in the power supply waveform enables energy recovery. HSPICE simulations show that the power consumption has been reduced by between 11.4 and 64.2%.

An accurate, very-high-output-resistance active-feedback cascode current mirror has been proposed and compared with a previously reported accurate cascode current mirror. Comparisons have shown that, besides higher accuracy and output resistance, the proposed circuit has no residual error, but has a wider output voltage swing, a much higher PSRR, and an easier and more flexible design.

Up to the present, the use of magnetic amplifiers has largely been confined to problems associated with the amplification of small quantities of D.C. power. In these cases, the A.C. supply to the device normally operates at power frequencies. This paper shows that the time constant of the amplifier is limited by the supply frequency, and then goes on to discuss the possibility of reducing the response time by operating the device from a supply frequency of about 20 kc/s. Results show that there is an optimum core size for a given frequency and power output, and that this optimum becomes more critical as the supply frequency is increased. Finally, it is shown from experimental results that the magnetic amplifier has distinct possibilities in the field of audio frequency amplification.

The PSRR (power-supply rejection ratio) in switched-capacitor (SC) circuits is dominated by clock feedthrough. As a result PSRR figures are typically too low for high-performance signal processing. A novel high-PSRR CMOS clock buffer, which effectively blocks this power supply (PS) noise coupling path, is presented. The circuit is a significant improvement over an earlier circuit proposed by the author (IEEE Int. Symp. on Circ. & Syst., p.68-71, May 1987), having with a simulated PSRR of over 40 dB. >

An integrated treatment of the input offset-voltage Vos, common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) of a simple resistively loaded bipolar differential amplifier establishes the basic theoretical relationships between these parameters and indicates that `Early-voltage´ mismatch of the constituent devices limits the attainable CMRR and PSRR.

Two novel CMOS single-ended amplifiers are presented. Suitable for switched-capacitor-filter designs, they exhibit high gain and bandwidth as well as high PSRR, low power and small size.

An experimental controller has the load in series with a resistance (or reactance), which is modulated within the supply cycle, such that the voltage drop at the supply frequency is eliminated. Control is effected by switching between this `on state? and a high-series-impedance `off state?.