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This paper studies the frequency tuning effect on the locking range property of a dual-resonance 3:1 injection-locked frequency divider (ILFD) fabricated in a foundry 0.18 μm BiCMOS process. The ILFD architecture is based on a capacitive cross-coupled oscillator in conjunction with a resistor-degraded dual-resonance resonator for the locking range improvement. At a power consumption of 5.26 mW and at injection power of P inj = 0 dBm the locking range from the measurement is from 6.2 to 12.6 GHz (68.09%). The frequency tuning range of the free-running ILFD shows a frequency tuning hysteresis effect; at low input power level the locking range shows bipolar locking ranges and at high injection power the locking range is independent of the measured voltage tuning direction.

This Letter proposes a divide-by-2 injection-locked frequency divider (ILFD) with a new passive resonator. The ILFD in the 0.18 μm 1P6M CMOS process uses a three-dimensional inductor consisted of three series single-path and multi-path inductors. Measured data shows that the varactor-less divide-by-2 ILFD has wide locking range, low power consumption and occupies a small area of 0.4446 × 0.9198 mm 2 .

This study describes the design and operation principle of quadrature voltage-controlled oscillator (QVCO) with complementary current-reuse (CR) voltage-controlled oscillators (VCOs). One CR complementary metal-oxide semiconductor (CMOS) VCO consists of a pair of p-type metal-oxide semiconductor field-effect transistors (pMOSFETs) and n-type metal-oxide semiconductor field-effect transistors (nMOSFETs), and an inductor. The other CR VCO consists of a pair of pMOSFET and heterojunction bipolar transistors (HBTs), and one inductor. The two CR VCOs are used to construct differential VCOs, which are subsequently used to build QVCOs coupled via coupling networks. The Bipolar-CMOS (BiCMOS) VCO and QVCO have been implemented with the Taiwan Semiconductor Manufacturing Company, Limited (TSMC) 0.18 μm SiGe BiCMOS technology. The CMOS QVCOs have been implemented with the TSMC 0.18 μm CMOS process. The quadrature phase generation and oscillation frequency equations are derived based on the block diagram of QVCO circuit.

A 2.48 GHz class-C voltage controlled oscillator (VCO) without any dynamic back bias circuit is presented. The VCO uses three-path high Q-factor inductor as the low loss resonator and class-C cross-coupled nMOSFET pairs for high dc/RF conversion efficiency and direct cross-coupled pMOSFET for dc current reuse. At the supply voltage of 1.2 V, the core power consumption is 0.24 mW. The phase noise of the VCO is −124 dBc/Hz and the VCO figure of merit is −197.0 dBc/Hz. The VCO was implemented in the TSMC standard 0.18 μm SiGe BiCMOS process and occupies a die area of 0.799 × 0.809 mm2.

A 2.5 GHz Class-C voltage-controlled oscillator (VCO) with dynamic back-gate-biased MOSFET is proposed. A dynamic gate biasing circuit is used to reduce power consumption by switching N-type MOS from initial Class-AB to Class-C operation in steady state. Moreover, the VCO uses dynamic back-gate bias to reduce threshold voltage of switching MOSFET during the start-up oscillation. The Class-C differential VCO is implemented in TSMC 0.18 μm bipolar-complementary-metal-oxide-semiconductor (BiCMOS) process. The measured phase noise is -124.8 dBc/Hz at 1 MHz offset frequency from 2.48 GHz carrier while consuming 2.64 mW power from a 0.8 V supply. Tuning range of VCO is 0.72 GHz, from 2.48 to 3.3 GHz, whereas the control voltage was tuned from 0 to 2 V. The VCO occupies a chip area of 446 × 840 μm 2 and provides a figure of merit of -197.55 dBc/Hz.

Conventional CMOS injection-locked frequency dividers (ILFDs) were often designed with a single-resonance LC resonator and they have a single-band locking range. Wide-locking range in these ILFDs was obtained at the cost of lower output power. A triple-resonance (TR) resistor (R), inductor (L) and capacitor (C)-tank ILFD is presented to design a wide-locking range CMOS divide-by-2 circuit, which is based on a cross-coupled n-core MOS pair. The TR ILFD has three overlapped locking ranges seen as one-band locking range at high microwave injection power and it has large output power. At the core power consumption of 6.76 mW and at the microwave input power of 0 dBm, the divide-by-2 TR ILFD achieve a maximum locking range of 5.77 GHz (105.2%) from 2.6 to 8.37 GHz.

A new circuit technique is proposed to enhance the locking range of divide-by-3 injection-locked frequency dividers (ILFDs) implemented using a standard 0.18 μm CMOS process. The ILFD uses a transformer feedback to increase the second harmonic and enhances the conversion efficiency of injection metal–oxide semiconductor field-effect transistor mixers. The ILFD core consumes 10.8 mW power at the supply voltage of 0.9 V and with a circuit core current of 12 mA. At the incident power of 0 dBm, the measured locking range is 4.2 GHz (37.17%), from the incident frequency 9.2–13.4 GHz.

A novel wide-locking range divide-by-3 injection-locked frequency divider (ILFD) is designed and fabricated in a standard 0.18 μm CMOS process. The CMOS ILFD uses a class-C capacitive cross-coupled oscillator as the core. It has been found that the locking range of the ILFD is enhanced when the DC-gate bias is smaller than the drain bias in the cross-coupled pair. At the supply voltage of 1.8 V, the core power consumption of the ILFD core is 10.7 mW. At the incident power of 0 dBm, the maximum locking range is 3.3 GHz (24.17%), from the incident frequency 12–15.3 GHz. At the incident power of 0 dBm, the operation range is 4.8 GHz (37.2%), from the incident frequency 10.5–15.3 GHz.

An enhanced locking range technique for a CMOS injection-locked frequency divider (ILFD) is presented, which uses a cross-coupled oscillator with a dual-resonance RLC resonator. This ILFD has dual locking ranges at a fixed bias, and the resistor in the resonator is used to have overlapping dual locking ranges so that a single-band wide-locking range is obtained. At the incident power of 0 dBm, the locking range of the divide-by-2 ILFD is 6.7 GHz, from 3 to 9.7 GHz, and the locking range percentage is 105.51%.

A new divide-by-3 injection-locked frequency divider (ILFD) is proposed. The ILFD consists of a 7.6 GHz voltage controlled oscillator (VCO) and two transformers, which are in series with the cross-coupled transistors in the VCO for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.13 m CMOS technology. At the supply voltage of 0.8 V, the core power consumption is 1.25 mW, and the free-running frequency of the ILFD is tunable from 7.2 to 7.87 GHz. At the input power of 0 dBm, the total divide-by-3 locking range is from 21.56 to 23.63 GHz as the tuning voltage is varied from 0.0 to 0.8 V. The phase noise of the locked ILFD output is lower than that of the free-running ILFD in the divide-by-3 mode.