1. Low‐jitter DLL applied for two‐segment TDC
- Author
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Lixia Zheng, Weifeng Sun, Rongqi Zhao, Kunpeng Zhang, Zhang Youzhi, and Jin Wu
- Subjects
Physics ,020208 electrical & electronic engineering ,Linearity ,02 engineering and technology ,Feedback loop ,Phase detector ,020202 computer hardware & architecture ,Root mean square ,CMOS ,Control and Systems Engineering ,Delay-locked loop ,0202 electrical engineering, electronic engineering, information engineering ,Charge pump ,Electronic engineering ,Electrical and Electronic Engineering ,Jitter - Abstract
A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal-oxide-semiconductor process, the measurement results show that DLL's frequency locking range is 60-240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of
- Published
- 2017