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Frequency division multiplexing has been studied as a means of communication between neural layers in an analogue multilayered perceptron neural network architecture, trained using the back-propagation learning algorithm. Simulation results on network learning and generalisation show that the neural network is tolerant to as much as 50% overlap of frequency responses of filters used in demultiplexing. Thus, the number of communication channels available is considerably increased.

This paper presents the results of research into a scheme for overcoming the communications 'bottleneck' within hardware neural networks, utilising frequency division multiplexing of amplitude modulated neural signals. The introduction explains the problem of connectivity in neural networks and the need for multiplexing, followed by an introduction to the FDM solution. A comparison of FDM with TDM is then presented which shows that it is necessary to allow a moderate amount of band overlap in the FDM channel, to utilise the available bandwidth effectively. This approach is possible by virtue of the inherent error tolerance of the neural system.

A novel analogue CMOS circuit is presented which performs the arithmetical squaring of a voltage, using the square-law characteristic of the MOS transistor in saturation. The core circuit is constructed from four identical building blocks, which are connected so as to eliminate all unwanted offset terms. Simulation results from HSPICE are presented where the circuit is used for doubling the frequency of a sinusoidal input.