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Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is proposed that is highly scalable, and can be easily changed to accomodate various needs. A network-on-chip design, realised as part of the platform that the authors are developing for reconfigurable systems, is presented. This design is suitable for building networks with irregular topologies, and with low latency and high throughput. [ABSTRACT FROM AUTHOR]

Presents the exploitation of loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling. Importance of coarse-grained reconfigurable architecture; Use of automatic design or compilation tools; Use of a reconfigurable embedded systems compiler.