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The channel length dependence of the stress-induced carrier velocity gain in linear and saturation operation regimes is investigated in uniaxially and biaxially stressed N-MOSFETs. Results indicate that, even though strained CMOS technology offers significant mobility gain (here 55% at maximum), saturation velocity effects strongly reduce its impact on the saturation region as manifested by the degradation of the velocity gain measured at high drain voltage. [ABSTRACT FROM AUTHOR]

A simple yet accurate delay model based on the method of logical effort is presented for the analysis of high-speed current-mode logic (CML) circuits. The model describes the logical effort of a CML gate in terms of its operating current density normalised to the characteristic current density that yields peak transistor cutoff frequency (fT). Since the latter remains largely invariant over technology nodes as a result of constant-field scaling, the proposed logical effort model quantifies the effect of gate sizing, biasing and loading to simplify delay analysis for CML gates. [ABSTRACT FROM AUTHOR]

Highly efficient power-gating systems beyond conventional CMOS technology could be realised using a new non-volatile flip-flop design based on a 'pseudo-spin-MOSFET' (PSMOSFET), researchers in Japan have shown. The non-volatile flip-flop architecture is faster and uses less power than other backup architectures using ordinary flip-flops, and is compatible with existing CMOS fabrication and circuit technologies. [ABSTRACT FROM AUTHOR]