1. Effects of Dit-induced degradation on InGaAs/InAlAs nanowire superlattice-FET using Al2O3 and HfO2/La2O3 as gate stacks
- Author
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MAIORANO, PASQUALE, GNANI, ELENA, GNUDI, ANTONIO, REGGIANI, SUSANNA, BACCARANI, GIORGIO, Maiorano, P., Gnani, E., Gnudi, A., Reggiani, S., and Baccarani, G.
- Subjects
Subthreshold characteristic ,Nanowire ,Low stand-by power ,Gate dielectric ,Off-state leakage ,Dielectric material ,Interface trap density ,Interface state ,Technology node ,Superlattice ,Nanowire superlattice ,Induced degradation ,Hafnium oxide ,Power performance ,Aluminum - Abstract
In this work we investigate the effects of different interface trap density distributions (Dit) on the electrical and power performances of a Gate-All-Around In0.53Ga0.47As/In0.52Al0.48As Nanowire Superlattice-FETs (GAA NW SL-FET) using Al2O3 and HfO2/La2O3 as gate dielectrics. This analysis shows that a high At content at the high-K/InGaAs interface causes degradation of the subthreshold characteristics and drive current, but also an improvement of the OFF-state leakage. However, even in the presence of traps, dynamic energy/power consumption of the Al2O3-based SL-FET is predicted to be at least 2× lower than all the ITRS requirements for the 9nm technology node, while HfO2/La2O3-based device is perfectly suitably for Low-Standby-Power application, at fixed supply voltage Vdd = 0.4 V.
- Published
- 2015