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In recent years, in the automotive sector, devices that need a regulated DC supply voltage have increased. DCDC switching converters are the best solution in terms of performance, cost, and efficiency. Among DCDC converters, the Step-Down switching converter (or Buck converter) is very important. The high number of these devices installed on a car requires the reduction of the cost for the system, with a very simple implementation, but maintaining comparable performances with a more complex and expensive design. In this article, an Asynchronous Constant TOFF Peak Current Mode Controlled (PCMC) Buck converter, with a maximum output current of 10A, is presented. Thanks to this type of Pulse Frequency Modulation (PFM) control and an integrated high-side current sensing, it is possible to realize an efficient system with over-current protection, duty cycle greater than 50%, without slope compensations, and high efficiency also at low loads. The implementation of the integrated current sense, the high switching frequency and the high stability of constant TOFF reduce at the minimum the number of external components and the used area for IC to lower the price of the buck converter system. The Quasi-Constant switching frequency allows using a cheapest filter for automotive EMI tests. The system works with a switching frequency around 1MHz with a precise output voltage from 1. 8V to 5V with an output current up to 10A.

This paper presents the complete design and electrical characterization of a SPICE model emulating the neuron membrane electrochemical behaviour. This constitutes an easy-to-use and compact tool that predicts action potential time-domain evolution, identifying the minimum input charge/second threshold that induces neuron electrical firing. Specifically, the cell membrane ionic channels are described by custom components in the Verilog-A Hardware Description Language. By stimulating the model using fast electrical charge pulses, it is possible to obtain action potentials signals perfectly consistent with the mathematical model based on Hodgkin-Huxley equations (or with electrochemical behaviour of the neuron cell membrane). The neuron circuit was validated by extensive transient simulations in Cadence. This tool, therefore, allows developing custom hardware for Neuroscience and Artificial Intelligence by easily integrating and simulating the biological environment in Electronic Design Automation (EDA) software.

This work presents the development and experimental validation of a ionacoustic detector that uses a multi-channel sensor, a dedicated ASIC in 28nm CMOS and hardware DSP to reduce the input-referred noise power by 1-2 orders of magnitude compared to state of the art ionacoustic detectors. The most interesting application of the ionacoustic technique is the real-time monitoring with sub-millimeter precision of hadron therapy treatments, but the main limitation of current detectors lies in their high latency and noise power, not compatible with clinical treatments. The hereby presented High-Resolution Proton Sound Detector exploits the parallel acquisition and processing of 64 channels to obtain a 2D acoustic image of the source with 256x256 pixel resolution, 140 fps and 70 mPaRMS input-referred noise, resulting in 34 dB SNR with 0.8 Gy dose deposition.

A 130-nm CMOS high-side current sensor (CS) for peak-current dc-dc converters, operating with an input voltage up to 40 V is presented. A loop prebiasing technique is used to prevent the proposed sense-FET-based CS from losing its linear behavior, thus achieving fast response time and, hence, allowing operation of the dc-dc converter with short minimum on-time. The proposed circuit also exploits a feedback resistance emulation technique for preventing the feedback loop to open during the blanking time. The CS has been integrated within a complete 40-V peak-current dc-dc buck converter that achieves 1-mV/A load regulation and 0.1-mV/V line regulation performances, even with a minimum on-time of 51 ns, with a peak efficiency of 92.5%.

This article presents a cross-domain model that defines and sets the acoustic signal generation process due to the fast dose deposition induced by a proton beam penetrating an energy absorber. The proposed model reduces the complex iono-acoustic energy transformation process to a simple impulse-response of a linear-time-invariant (LTI) system and is validated by comparing LTI output simulation results (in both time and frequency domain) with experimental acoustic signals emitted by a physical proton beam at 20 MeV and 70-120-ns pulse time width. Thanks to the intrinsic simplicity of the system, it is possible to predict and estimate the effective acoustic power at the sensor and the resultant beam range measurement precision. More importantly, the information coming from LTI simulations provides well-defined methodologies that allow to increase acoustic signal amplitude from +3 up to +9 dB and to improve the measurement precision of the beam range localization (up to +/ - 0.3 mm versus +/ - 0.6 mm state of the art for 200-MeV energy and 75-mGy total dose).

Proton sound detectors rely on sensing the weak thermoacoustic signals emitted by the fast energy deposition at the end of the beam penetration path through the energy absorber. The energy of the ions/protons is first converted into heat, and then, into pressure by a thermodynamic process. The pressure signal propagates through the energy absorber, and it is read by an acoustic sensor, which, in turn, converts the pressure wave into an analog electrical voltage. Such an analog signal is digitalized by the analog front-end. Its digital representation is used for the measurement of the beam depth. This emerging technique attracts attention in both physics experiments and medical applications (hadron therapy). This article investigates the signal-to-noise-ratio performance in proton sound detectors exploring all critical steps that lead to both reduction of the power of the electrical signal and noise power increasing. Nonetheless, this article proposes specific technical solutions to mitigate such signal-to-noise-ratio degradations with particular attention to higher energy (i.e., 200 MeV) proton beams, which are crucial for medical applications, and where the maximum achievable signal-to-noise ratio can be 50/60 dB lower than 20 MeV acoustic pulses.

This paper presents a fully integrated 65nm CMOS Low-Dropout (LDO) voltage regulator for MEMS devices in the microphone field. The proposed LDO exploits a nested loop to generate the regulated voltage. The external loop generates a precise mathbf{V}_{mathbf{out}} and the internal loop gets a fast transient response by means of a Flipped Voltage Follower (FVF). To achieve a high Power Supply Rejection (PSR) a Tail compensated Error Amplifier (EA) was used. Powered by a {1.8mathrm{V}pm 10%} VDD, the LDO provides a 1.2V regulated voltage in the whole temperature range {[-40, 85]{circ}mathrm{C}} while consuming a quiescent current of 8.7uA (15. 7u W of nominal power consumption). It is capable of driving from 200uA to 800uA of static current load without affecting performance. The LDO occupies an active area of {0.0363text{mm}{{2}}} {(0.3text{mm x} 0.121text{mm})} including the 70pF on chip capacitor. This means that the LDO can be used in a System on a Chip (Soc) thanks to the absence of an off-chip capacitor. The simulation shows a PSR {< -70text{dB}} in the audio band ([20, 20k]Hz), a PSR peak below -10dB and a fast transient response of 148ns. Furthermore, Montecarlo and PVT simulations show the robustness of the circuit. Worst cases prove that the mathbf{V}_{mathbf{out}} value never exceeds {1.2mathrm{V}pm 5%} during DC and transient analysis. The overall mathbf{V}_{mathbf{out}} error is 0.3%.

An electrostatic discharge (ESD)-protected one-time-programmable (OTP) memory front-end circuit, for high-voltage (HV) applications, designed and manufactured in silicon-on-insulator (SOI) technology, is presented. The SOI technology meets HV functional-isolation and level-shifting requirements but is not suitable for advanced analog circuits. The presented OTP memory is discussed as an introduction to digital programmability in the considered technology. The memory element consists of an antifuse type structure and is implemented using a 5-V nMOS with L=1µm and W=1.2µm. The cell memory allows for significant area and power savings in the adopted HV technology. Conditions for this require that an efficient ESD protection will guarantee safe operation, even in the presence of a small and fragile on-chip element whose undesired burning would compromise the programming mechanism, and consequently the reliability, of the circuit. Details about the circuit design implementation of the front-end circuit for both read and write circuits and ESD protection are described with experimental results validating the proposed implementation.

This article presents a fully analog, signal-to-noise-ratio-based voice-activity detection (VAD) circuit. The circuit is based on an energy-efficient analog implementation with continuous-time nonlinear operation and fully passive switched-capacitor signal processing. The overall chain is composed of a programmable-gain amplifier, a squarer, an integrator, an SC-based signal averaging circuit, and a periodic threshold update circuit for adaptability. This implementation allows the minimization of both power consumption and chip area. The VAD circuit prototype has been fabricated in a 180-nm CMOS technology and occupies an area of 0.14 mm². The device achieves 99.5% classification accuracy in a domestic environment in the presence of loud ambient noise, consuming 760 nW from a 1.2-V supply.

The paper presents an upgrade of the Peak Current Mode Control (PCMC) for a Buck DC-DC Converter. Constant Off-Time algorithm has a fixed off-switch phase, and, conversely to the typical PCMC, the duration of the switching period is free to change depending on the load and the battery voltage. In this way the instability issues, typical of a PCMC, are solved. The circuit is able to robustly sink 3 ± 5%A average current from a car battery source, in a 3.5 V output voltage - 212kHz maximum frequency application. In addition, the circuit intrinsically provides protection against over-current and allows precise control over the current features (peak, average and ripple). The concept will result in a fully integrated system without external pad to sense the current, thanks to the proposed integrated sensing technique. The power consumption is also reduced since the current is read only during the on-switch phase.

This work presents the design and experimental validation of a photoacoustic setup that emulates the acoustic signal generated by a 20 MeV proton beam by ionoacoustic effect. This system serves as a practical tool to experimentally test ionoacoustic detectors in a simple yet representative setup prior to performing beam tests at accelerator facilities. To emulate the ionoacoustic effect the hereby presented Proton Sound Detector Testbench (ProSD-TB) uses a 70 W peak power pulsed laser and a specifically designed target absorber. The experimental validation of the ProSD-TB shows that it is capable to emulate a 20 MeV proton beam ionoacoustic signal in terms of signal amplitude (few Pa at the sensor surface) and frequency (2 MHz). The time domain signal generated by the ProSD-TB is acquired by means of a 64-ch Proton Sound Detector composed by a multichannel acoustic sensor, a dedicated analog front-end and signal processing. The ProSD-TB is validated against a 20 MeV ionoacoustic signal both in time domain and by comparing the 20 MeV dose deposition profile to an acoustic image generated by the Proton Sound Detector.

This paper presents the sensitivity analysis of an extended-range, second-order Incremental ADC (IADC) to the non-idealities of the operational amplifiers (op-amps) used. Different configurations of the extended-range IADCs are compared in terms of required ENOB and op-amp specifications. In all the configurations, a flash ADC with varying resolution is used as extended-range ADC. The ADC clock frequency is considered in all cases equal to 80 MHz. From the analysis it turns out that, in order to achieve a given ENOB, the extended-range IADC requires a significantly lower number of clock cycles than a conventional IADC, but the requirements of the op-amps are much more stringent.

Most of the motor driving systems are still using IGBTs as power switches. Switching efficiency - strictly related to switching losses and switching frequency - is of the utmost importance at system level. IGBTs are traditionally driven using a fixed output current, but this solution does not take into account Miller Capacitance (Crss) non-linearity effects. As Crss value spreads of one or even more order of magnitude over the collector-to-emitter voltage (VCE) swing, the fixed current produces two different dV/dt on the inverter output. This affect switching performances increasing switching losses, due to a slow transient of the IGBT's gate and VCE, and reducing the possibility of increasing the switching frequency. In order to solve this issue, a two-step gate driver is proposed in this paper, with a focus on experimental results. The proposed solution has been implemented in an integrated circuit developed in a $1 {mu} mathrm{m}$ High Voltage (HV) SOI technology. Concept, circuit's features and bench results are presented, highlighting the advantages of this solution and defining future improvements.

This paper presents a fully analog, signal-to-noise ratio (SNR) based voice-activity detection circuit, which achieves 99.5 % classification accuracy in a domestic environment in the presence of loud ambient noise, consuming 760 nW from a 1.2 V supply. The circuit exploits an energy-efficient analog implementation with continuous-time non-linear operation and fully-passive switched-capacitor processing, to minimize both the power consumption and the chip area. The VAD circuit prototype, fabricated in a 180 nm CMOS technology, occupies 0.14mm2.

The demand for low-cost integrated circuits for automotive applications is increasing, while their cost must remain low to maintain product competitiveness. In this scenario, to guarantee DC-DC Buck converters high-efficiency and low cost (in terms of external components) increasing switching frequency is mandatory. The main problems are inherent the parasitic inductances and the parasitic capacitance of power MOSFET. This paper deals with the main critical aspects of increasing such switching frequency and show how to replace the external Schottky diode with an integrated structure. The case of a highspeed monolithic integrated circuit to control a load current is here proposed. Proper design allows to achieve switching frequency up to 1MHz with 94.4% efficiency.

Total ionizing dose (TID) mechanisms are investigated in 28-nm MOSFETs via dc static and low-frequency noise measurements. nMOSFETs and pMOSFETs are irradiated up to 1 Grad(SiO2) and annealed at high temperatures. TID sensitivity depends on the channel length, the channel width, and the bias condition. Halo implantations improve the radiation tolerance of shorter-channel transistors. Worst case bias for TID-induced degradation is found with high electric field applied to the gate during irradiation, due to increased charge trapping in the upper corner of the shallow trench isolation (STI) and in the gate oxide. DC and low-frequency noise measurements show that, at doses up to 100 Mrad(SiO2), radiation-induced degradation is primarily due to the positive charge buildup in the STI oxides. At ultrahigh doses approaching 1 Grad(SiO2), TID degradation is influenced by charge buildup in the gate oxide and traps at or near the gate/dielectric interface and/or along the STI sidewalls. Worst case degradation is found in narrower and longer-channel devices, due to the enhanced charge buildup in the STI oxide and along its interfaces.

This work presents a read-out amplifier for capacitive sensors, in particular for MEMS microphones, based on a current-feedback topology. This architecture allows for an extensive gain range while keeping the input impedance as well as the amplifier bandwidth independent of the selected gain. Noise performance is maximized and signal attenuation due to parasitic effects is minimized and stays constant at all gain settings. This architecture has been used for the design of an interface circuit for a MEMS microphone in a standard 0.13 mu m CMOS process.

The demand for low-cost integrated circuits for automotive applications is increasing, while their cost must remain low to keep the product competitive. In this scenario, a high-speed monolithic integrated circuit to control a load current is here proposed. It is composed by a level shifter and a gate driver for a high power switch in a DC-DC Buck converter to be realized in a low cost technology. For chip area reduction, an n-channel vertical power transistor is chosen as power transistor. High switching frequency (up to 1MHz) can be used to reduce external components size. The device is optimized to achieve 94.4% efficiency. Implementation concept, schematic and layout will be shown.

A Fast Tracker analog front end for small-diameter Muon Drift Tube (sMDT) detectors is hereby presented. The analog channel has been integrated in 28 nm CMOS technology and significantly improves state-of-the-art sMDT read-out systems thanks to a novel signal processing technique exploited to extract information from sMDT detectors speeding-up the processing time and to limit fake events detection. The main idea is to implement a fast reset of all continuous-time analog stages that occurs just after the charge (i.e. event) detection. This has two main advantages for sMDT read-out: fast processing and negligible signal corruption due to non-relevant pile-up signals. Nonetheless, the realization in 28nm bulk-CMOS technology implies challenges for analog design but advantages in terms of speed, area occupancy and radiation hardness. The proposed analog channel occupies 0.03 mm2 and consumes 1.9 mW from 1 V supply voltage.

This paper presents the complete design, the hardware implementation, and the experimental validation of a distributed intelligence Internet-of-Things (IoT) system, based on Heterogeneous Event-Driven Edge Mesh Architecture (HED-EMA). The latter differentiates from most common computational schemes (i.e. Cloud computing) since it distributes intelligence at local level. The proposed IoT system has a bottom-up structure composed by three main layers: Sensing/Actuation, Edge, and Cloud. It exploits commercial devices, specifically programmed and configured in order to operate within the IoT paradigm. Aiming to validate the proposed system, experimental data coming from two specific setups (home-setup and automotive-setup) will be presented and discussed. Data are extracted by a distributed sensors network, real-time collected, and processed. The lower response time compared to standard Cloud architectures and the whole system power consumption reduction are then demonstrated.

This paper presents the design and the experimental validation of a 6th-order continuous-time low-pass filter in 28 nm bulk-CMOS,based on the cascade of 3 Rauch biquadratic cells. Each cell exploits a broad-bandwidth Operational Transconductance Amplifier (OTA),without Miller compensation scheme for differential Loop Gain stability. This maximizes the OTA unity gain bandwidth,with no power increase w.r.t classical compensation schemes,and improves both frequency response accuracy and linearity over the filter pass-band. This aggressive design choice is sustained by the higher 28 nm CMOS transistor's transition frequency and by the intrinsic feature of the Rauch cell,whose R-C feedback/direct path nets introduce two poles and two zeros that self-compensate the differential loop-gain. On the other hand,the proposed OTA only exploits a compensation scheme for the common-mode signal stability,which does not affect the differential signal. The prototype synthesizes 50 MHz low-pass frequency response at 3.3 mA current consumption from a single 1.1 V supply and performs 18 dBm and 16.5 dBm Input IP3 for 1011 MHz and 4041 MHz input tones,equalizing the linearity performance over the filter pass-band,just thanks to the OTA wider bandwidth. This finally allows 153 dBJ-1 and 158 dBJ-1 Figure-of-Merit at 1011 MHz and 4041 MHz input tones.

In this paper, the total ionizing dose (TID) response of a commercial 28-nm high-k CMOS technology at ultrahigh doses is measured and discussed. The degradation of pMOSFETs depends not only on the channel width but also on the channel length. Short-channel pMOSFETs exhibit a higher TID tolerance compared to long ones. We attributed this effect to the presence of the halo implantations. For short-channel lengths, the drain halo can overlap the source one, increasing the average bulk doping along the channel. The higher bulk doping attenuates the radiation-induced degradation, improving the TID tolerance of short-channel transistors. The results are finally compared and discussed through technology computer-aided design simulations.

This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of n MOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual n MOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the drain leakage current. We introduce a semiempirical physics-based approach using only three parameters to model the parallel parasitic and total drain leakage current as a function of TID. Taking into account the gate independence of the drain leakage current at high TID levels, we model the lateral parasitic device as a gateless charge-controlled device by using the simplified charge-based Enz-Krummenaker-Vittoz (EKV) MOSFET model. This approach enables us to extract the equivalent density of trapped charges related to the shallow trench isolation oxides. The adopted simplified EKV MOSFET model indicates the weak inversion operation of the lateral parasitic devices.

Using the Y-function method, this paper experimentally investigates the effects of total ionizing dose up to 1 Grad on the channel mobility of a commercial 28-nm bulk CMOS process.

This paper investigates the effects of total ionizing dose up to 1 Grad on 28-nm bulk MOSFETs under different bias conditions during irradiation. The aim is to assess the potential use of this commercial bulk CMOS technology in the future high-luminosity Large Hadron Collider at CERN that will require highly improved radiation-tolerant tracking systems.

This paper presents the development of an Internet-of-Things (IoT) Cooperative System (IoT-CS) based on local Event-Driven response. After introducing IoT basic concepts and most common computational schemes (with particular attention on the differences between Cloud, Fog, and Cooperative computing paradigms), an innovative scheme for IoT will be presented. Thanks to the introduction and development of several intermediate layers between the sensor network and the Cloud, the hereby proposed system allows overcoming most of the problems of the state-of-the-art paradigms. In order to validate the proposed solution the most relevant aspects of this implementations will be presented.

Clinical proton and ions beams for cancer treatment provide maximum energy deposition (Bragg Peak, BP) at the end of their range and practically no dose behind. This enables a more efficient therapeutic option comparing with classical photon-based radiotherapy where maximum energy deposition occurs at the body/tissues interface. Obviously, optimum/minimum-error BP detection and calibration is thus a key aspect of this treatment. This work investigates a promising detection technique, based on the so called (proton) iono-acoustic effect. The BP energy deposition causes a small (mK) heating of the surrounding region that in turn induces a pressure variation. This propagates an ultrasound signal (MHz range) whose time-of-flight measurement aims to detect the BP position with very high accuracy (<1mm). This paper presents the simulation results of complete mixed-signals and mixed-energies model that starting from proton beam energy calculates the induced pressure variation in water, emulates the propagation of sound waves in the medium and finally provides a voltage signal (including noise) whose time evolution determines BP position.

This paper presents the results of a multidisciplinary experiment where the electrical activity of a rat hippocampus cultured neurons population has been detected and mapped by an advanced FPGA spike-sorting algorithm. Neurons are growth over a silicon chip that is thus capacitively coupled with neuronal cells. Due to noise power coming from bio-silicon interface and analog electronics signal processing, the Action Potentials detection intrinsically needs advanced noise rejection algorithms which are often software/off-line implemented. This approach disables instantaneous detection of neural spikes and cannot be obviously used for real-time electrical stimulation. In this scenario, this paper presents a proper FPGA system able to separate relevant neuronal cells potentials from noise. The FPGA output signals provide real time spatial mapping of biosensor electrical activity, noise and synchronous neural network activity.

This paper presents the result of a multidisciplinary experiment where electrical activity from a cultured rat hippocampi neuronal population is detected in real time by a FPGA implemented digital circuit. State-of-the-art EOMOSFET Multi Electrode Array (MEA) biosensors exploits a capacitive coupling between the biological environment and the sensing electronics to minimize invasiveness and cell damage, at the price of a lower SNR. For this reason, they are typically improved by noise rejection algorithms. Real time neural spikes detection opens unthinkable scenarios, allowing to stimulate single neurons in response to their behavior, possibly improving medical conditions like epilepsy. In this scenario, a spike sorting algorithm has been hardware implemented, allowing real time neural spike detection with a latency of 165ns

Clinical ions beams for cancer treatment provide maximum energy deposition (Bragg peak (BP)) at the end of their range and practically no dose behind. This enables a more efficient therapeutic option comparing with classical photon-based radiotherapy where maximum energy is deposited at the body interface. Obviously, minimum-error BP detection is, thus, a key aspect of this treatment. This paper investigates a promising detection technique, based on the so-called ionoacoustic effect. The BP energy deposition causes a small (millikelvin) heating of the surrounding volume that in turn induces a pressure variation. This generates a sound signal that can be detected by an acoustic sensor placed at a certain distance from the BP point. Thus, the sound time-of-flight measure aims, with sound speed, to detect the BP position with very high accuracy (<1 mm). This paper presents the results of a complete cross-domain model that starting from proton beam energy provides the induced pressure variation in water, emulates the propagation of sound waves in the medium, and finally, returns a voltage signal whose time evolution determines BP position with an average deviation from effective position of 1% accuracy.

In this paper a 75MHz 4th order low-pass analog filter in CMOS-28nm is presented. The filter is composed by the cascade of two Active-RC Rauch biquadratic cells. The hereby proposed design manages a very low Vdd/Vth ratio (<2) for Standard-Process (SP) MOS transistors by means of a dedicated input Common-Mode (CM) feedback circuit (I-CMFB), that operates the OPAMP input differential pair in weak inversion region independently on common mode variations. The single Rauch cell exploits a feed-forward compensated OPAMP, where an improved output CM feedback (O-CMFB) circuit has been adopted reducing this way the parasitic poles of the CM loop, and improving O-CMFB phase margin. The OPAMP has been designed using a folded topology for stable operating point. The design prototype achieves 75MHz-3dB frequency at 2.8mW power consumption from a single 0.9V supply voltage, including also I-CMFB and O-CMFB power. In-band integrated noise is 320uVrms. The filter performs 20dBm and 13dBm IIP3 at 6&11MHz and 50&55&MHz, respectively. Thanks to the very large linearity achieved at edge of the signal pass-band this design has one of the highest Figure-of-Merit for Active-RC filters.

This paper compares two CMOS technologies, the robust 350nm version and its modern 28nm successor, in terms of time-domain signal processing parameters. The evaluated parameters; propagation delay, delay variation due to process and mismatch fluctuations, sensitivity to noise and area and power usage are crucial especially in measurement devices relying on precise timings, high precision time-to-digital converters, for example. Post-layout simulations show that the modern scaled technology offers superior speed, efficient area usage and low power consumption but suffers from considerable delay mismatch. Therefore applications relying on precise time domain signal processing do not always benefit from technology scaling.

This paper presents a 14-bit 1MS/s extended range incremental A/D converter composed by the cascade of two resettable second-order sigma-delta modulators in 28nm technology. The system is designed for applications in instrumentation electronics for particle physics. Design of the converter is reported, including feasibility study and switched capacitor implementation. Architecture simulation results including non-idealities are reported. The developed A/D converter will be used for ultra-scaled technology (28nm) radiation hardness study in high energy physics experiments.

A pair of completely integrated capless preamplifiers (not requiring external capacitance) for MEMS microphones are presented. The devices exploit specific circuit solutions to implement a proper dc biasing of the pre-amplifier and a low frequency (< 1 Hz) high-pass pole. The two solutions adopted are a based on a transistor in the off state (OTP) and a switched-resistor (SRP), respectively. Since the devices are supposed to operate with different silicon microphones, the pre-amplifier gain has to be programmable. In spite of the single ended configuration and independently of the gain, both pre-amplifiers achieve a signal to noise ratio (SNR) lower than -100 dB. The total harmonic distortion (THD) is lower than -80 dB for the OTP and lower than -100 dB for the SRP. The devices are implemented in a 0.18-μm CMOS technology, with a supply voltage of 1.8-V. In both cases the power consumption is 230 μW. The bandwidth of interest ranges from 20 Hz to 20 kHz. Both solutions have variable gain configurations [-6, 0, 6, 12, 18] dB.

The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS technology in the forthcoming upgrade of the Large Hadron Collider at CERN. The total ionizing dose effects show limited influence in the drive current of all the tested nMOSFETs. Nonetheless, the leakage current increases significantly, affecting the normal device operation of the nMOSFETs. These phenomena can be linked to the charge trapping in the oxides and at the Si/oxide interfaces, related to both the gate oxide and the shallow trench isolation oxide. In addition, it has been observed that the radiation-induced effects are partly recovered by the long-term post-irradiation annealing. To quantify the total ionizing dose effects on DC characteristics, the threshold voltage, subthreshold swing, and drain induced barrier lowering have also been extracted for nMOSFETs.

The Total Ionizing Dose (TID) levels foreseen after the future upgrade of the CERN Large Hadron Collider (High Luminosity LHC) will heavily influence the performance of the electronics. A TID level of 1GigaRad will be accumulated in the innermost layer of the pixel detector in 10 years of operations, which could damage the readout circuits behavior with important failures in the experiments. To prevent this situation, the choice of a proper technology for the readout ASICs represents a key point. This paper deals with the characterization of single transistors and of an analog circuit, both realized in a TSMC 28nm bulk CMOS technology, after being irradiated with 1 GigaRad TID. nMOS devices result more resistant than pMOS showing a weak degradation of the electrical parameters. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as that hereby presented. In the proposed analog circuit, the high radiation level induces a 20% gain reduction and an 80% slowdown of the Charge Sensitive Preamplifier time response.

This paper presents the development of a mixed-signal multi-functional system for current measurement and electrical stress detection. The system is composed of a tracking ADC and a double range (a coarse and a fine one) current-steering DAC. The coarse range, designed for the full-scale input values [0A:108A], has a 5b resolution and it is used for the stress detection feature. The fine range is for lower input current values [4A:14A] and it is used for the current measurement, where more accuracy is required. With respect to the full-scale, the resolution of the fine range is 8b.

The GEMINI front-end system that will operate at LoKI experiment at ESS is expected to be exposed to radiation for a Total Ionizing Dose (TID) up to 200krad during Triple-GEM detector usage. Analyzing the effect of ionizing radiation on chip gives important information on its robustness, critical for architecture validation. After irradiation with a total dose of 15 Mrad core elements of GEMINI channels still resulted to be functional. This indicates the possibility of using such devices also in other experiments where it would be exposed to higher TID. The test also highlighted few critical points of the architecture that could be starting point to improve Triple-GEM front-end system radiation hardness.

This work lies within SCALTECH28 project, whose main purpose is to investigate the performance of the 28nm technology in terms of signal processing quality, power consumption, and radiation hardness for applications in instrumentation electronics for particle physics with respect to previous technological generations. An additional target is to experimentally evaluate radiation damage effects on single devices and on full circuits to develop rad-models for simulations. A test chip including elementary device arrays and dedicated read-out circuits has been developed and fully characterized. In particular, a capacitance to frequency converter has been integrated to measure the matching between different capacitors of a programmable array. Experimental results show that matching performance is comparable to previous technologies, making the 28nm technology eligible for analog signal processing in front-end circuits for physical experiments and related data converters. Samples have been sent to irradiation facility for high energy experiments compliance verification.

This paper investigates the radiation tolerance of 28-nm bulk n and p MOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28-nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex interplay of oxide and interface charge trapping relevant to the gate-related dielectrics and the shallow trench isolation. The narrowest/longest channel devices have the most serious performance degradation. In addition, n MOSFETs present a limited on-current variation and a significant off-current increase, while p MOSFETs show a negligible off-current change and a substantial on-current degradation. The postirradiation annealing annihilates or neutralizes oxide trapped positive charges and tends to partly recover the degraded device performance. To quantify the effects of TID and postirradiation annealing, parameters including the threshold voltage, the free carrier mobility, the subthreshold swing, and the drain-induced barrier lowering are extracted.

This brief presents a novel biquadratic cell (biquad) based on the flipped-source-follower (FSF) circuit. The main idea is to exploit the FSF circuit as a basic building block for a low-pass second-order filter, taking advantage of its well-known strengths, like low-output impedance, low-noise, large in-band linearity, and low power. Thanks to the very essential FSF circuit, the resulting biquad is a power-efficient broad bandwidth stage, with very low-noise performance. In order to validate the biquad design idea, extensive circuital simulation results will be presented. The filter design example synthesizes a third-order low-pass transfer function and consumes 2.3 mW from a single 1.8 V@VDD. Input noise spectral density is 7 nV/vHz. Linearity has been evaluated in terms of IIP3 (25 dBm) and THD (-40 dBc at 380 mV0-PEAK output voltage swing, resulting in 62-dB SNR). Hence, a very promising figure-of-merit (i.e., 165 J-1) has been achieved.

Mixed-signal speech processing system has been used in microphone-embedded portable electronics. Speech codec is the core of such a system. In speech codecs, sigma-delta modulator is one key block which converts analog voice signal into pulse density modulation (PDM) output for further digital signal processing. This paper shows the design of a triple-mode switched-capacitor sigma-delta modulator for speech codec. High mode (20 kHz signal bandwidth), low mode (4 kHz signal bandwidth), and sleep mode are implemented by addressing a flexible operation current. In order to realize a fully integrated solution, power management circuits dedicated to the modulator are also implemented, which includes frequency detector, LDO, bandgap and reference voltage buffers. The ASIC is fabricated in a 0.18-um CMOS process. In high mode measurement, an A-weighted signal-to-noise ratio (SNR) of 78 dB with -2.5 dBFS input is achieved under 138 uA. In low mode measurement, an SNR of 78 dB with -2 dBFS is achieved under 100 uA. In the standby condition, a sleep mode with current less than 10 uA is realized, so that the battery life is extended.