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We have developed an integration technology for the single electron transistor (SET)/CMOS hybrid systems. SET and CMOS transistors can be optimized without any possible degradation due to mixing dissimilar devices by adopting just one extra mask step for the separate gate oxidation (SGOX). We have confirmed that discrete devices show ideal characteristics required for the SET/CMOS hybrid systems. An SET shows obvious Coulomb oscillations with a 200-mV period and CMOS transistors show high voltage gain. Based on the hybrid process, new hybrid circuits, called periodic multiband filters, are proposed and successfully implemented. The new filter is designed to perform a filtering operation according to the periodic multiple blocking bands of which a period is originated from the SET. Such a novel function was implemented efficiently with a few transistors by making full use of the periodic nature of SET characteristics.

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0/spl times/10/sup 14//cm/sup 2/ and 2.0/spl times/10/sup 14//cm/sup 2/. Initial O/sub 2/ injection method was applied for gate oxidation. The method is composed of an O/sub 2/ injection/N/sub 2/ anneal/main oxidation, and the control process is composed of a N/sub 2/ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 /spl mu/m have been fabricated by use of the method. Compared to the control process, the initial O/sub 2/ injection process increases the amount of nitrogen piled up at the Si/SiO/sub 2/ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved.

A 0.25-/spl mu/m, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm/sup 2/ silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test.

A first multilevel vertical-channel silicon-oxide-nitride-oxide-silicon (MLVC-SONOS) memory cell is proposed and fabricated using 0.12-μm silicon-on-insulator (SOI) standard logic process for Flash memory cell with ultrahigh density. If NAND array structure is used, the unit cell size of MLVC-SONOS is 4F2. Further reduction of cell size is possible by using the multilevel concept which is originated from the steady states by two carrier transports from both the substrate and the gate. The program threshold voltages and their windows are uniform and controllable depending on the negative gate bias conditions. In addition, we propose a new endurance measurement method for multilevels and report the retention characteristics for multilevel memory operation.

The effect of deuterium on hot-carrier reliability of fully processed 0.18 /spl mu/m silicon-on-insulator (SOI) devices is investigated. The improvement of device lifetime by a factor of 30 is achieved by passivating the interface defects with deuterium instead of hydrogen. The hydrogen/deuterium isotope effect (/spl gamma/), defined as the ratio of generation interface traps of a hydrogenated device to that of a deuterated one, shows strong dependence on the gate stress voltages (V/sub gs/). Increasing V/sub gs/ results in the decrease of /spl gamma/. These results suggest that the breaking of Si-H(D) bonds by channel electrons through the vibrational heating mechanism may play an important role in the degradation of deep submicron SOI devices.

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V/sub gs/ stress, HEIP is found to dominate the shift of threshold voltage V/sub t/. When V/sub gs/ increases to a moderate value, the V/sub t/ shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V/sub gs/ is increased further to V/sub gs/=V/sub ds/. For the first time, the effects of interface trap creation and oxide charge trapping on the V/sub t/ shift are quantified by the proposed technique.

We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO/sub 2//Si interface. We have achieved a significant lifetime improvement (90/spl times/) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.

The giant deuterium isotope effect found previously for NMOS hot electron degradation is applied to study defect generation at the Si-SiO/sub 2/ interface. The data suggest that interface defects related to hydrogen depassivation may be generated directly by channel hot electrons bombarding the interface without the necessity of injection into the oxide. This is in contrast to the standard teaching that energetic holes, created by impact ionization, and injected into the oxide are the main cause for hydrogen-related defect generation at the Si-SiO/sub 2/ interfaces.