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This paper presents a 433 MHz low-power receiver utilizing an N-path filter technique and a self-frequency tracking mechanism. Without the front-end amplifier, the mixer-first architecture can reduce power consumption significantly. A self-adjusted frequency tracking loop (SA-FTL) adjusts local oscillator (LO) frequency to approach input RF frequency automatically, thereby enhancing conversion gain and lowering return loss. The receiver, implemented in a $0.18~\mu \text{m}$ CMOS process, achieves a sensitivity of −80 dBm at a bit error rate (BER) of 10−3 and a data rate of 10 kb/s, while consuming $152~\mu \text{W}$ from a 0.8V voltage supply.

In this paper, based on simple quadratic matrix algebra, feedback linearization and neural network methods, the kinematics and almost perturbation decoupling and tracking performances of nonlinear spacecraft attitude control represented by improved Rodriguez parameters are studied. A nonlinear robust attitude controller is proposed to ensure the global stability and the almost disturbance decoupling performance without any learning or adaptation rules used in neural network approach and without having to solve the complex Hamilton-Jacobi equation of H-infinity control approach. This study presents an example that cannot be solved by the first paper on the problem of almost disturbance decoupling, to illustrate the point that this method can easily solve the tracking and almost disturbance decoupling performance. In addition, we propose a novel algorithm and two theorems that design a controller with almost disturbance decoupling and tracking performances. On the basis of meeting the standards we proposed, we successfully carried out some simulations on the spacecraft system to solve the effects of external disturbance torques.

—It has been tough for the sports industry and the athletes during the COVID-19 pandemic, but in Taiwan, we have been lucky to contain the pandemic to a level that we could hold the 2021 National Intercollegiate Athletic Games (NIAG) in early May. We formed a Sport Technology Team of more than 30 scholars, students, and engineers to provide novel systems and solutions that make the athletic games rich of sport technologies. Some of the features could be the first time shown to the internet audience for large-scale athletic games. The technologies involved include table tennis ball trajectory and bounce distribution, badminton shuttlecock tracking and trajectory, augmented reality enriched content for real-time video streaming on social networks, real-time 3D broadcasting with wide-field free viewangle, in-stadium video stream pushing by private 5G network with Mobile Edge Computing (MEC), AI-based sport data analytics during live streaming, a Technology-Enhanced Broadcasting System for sport events, etc. This paper introduces the respective technologies that we have developed, deployed, and demonstrated in the 2021 NIAG, Taiwan. We stress the architecture design and integration of TBS, which is a System of Systems, as well as experimental results on real athletic games in the smart stadiums that we have established.

This paper presents an optically-powered wireless tag, integrating a charge pump (CP) and a low-power RF transmitter for batteryless Internet-of-Things (IoT) applications. The proposed charge pump with hysteresis regulation mechanism (HRM) powers the transmitter circuit using indoor light energy. The charge pump enables the transmitter whenever the output capacitor stores sufficient energy and guarantees a short period signal transmission. The proposed low-power transmitter contains the subharmonically injection-locked PLL and the capacitive coupling technique to achieve a large frequency multiplication ratio. The proposed batteryless wireless chip is fabricated in 0.18- $\mu \text{m}$ CMOS process. The measurement results demonstrate that the proposed charge pump provides a 1.1 to 1.3 V hysteresis regulated voltage under indoor light illumination larger than 300 lux. The charge pump achieves 84.1% peak efficiency and the communication distance of 3 meters is demonstrated while only consuming $248~\mu \text{W}$ .

An inductive load test circuit was used to measure the switching performance of fieldplated edge-terminated Schottky rectifiers with a reverse breakdown voltage of 760 V (0.1 cm diameter, 7.85 × 10-3cm2 area) and an absolute forward current of 1 A on 8 μm thick epitaxial ß-Ga2O3 drift layers. The recovery characteristics for these vertical geometry ß-Ga2O3 Schottky rectifiers switching from forward current of 1 A to reverse off-state voltage of -300 V showed a recovery time (trr) of 64 ns. There was no significant temperature dependence of trr up to 150 °C.

Growing demand for key-value store applications is building a strong momentum for the commercialization of key-value hard disk drives. To achieve better performance, flash-based solid state drive is the next ideal candidate for commercialization in the foreseeable future. However, the existing fixed-sized management strategies of flash-based devices would potentially result in low storage space utilization when managing variable-sized key-value data. In addition, the low storage space utilization would further lead to the degradation of device performance, due to low invalid data space reclamation efficiency. The space utilization issue motivates this paper to propose a key-value flash translation layer design to improve storage space utilization as well as the performance of the key-value solid state drives. A series of experiments was conducted to evaluate the proposed design, and the experiment results of space utilization and device performance are very encouraging.

The growing demands of large-capacity flash-based storages have facilitated the downscaling process of NAND flash memory. However, the downscaling of traditional planar floating-gate flash memory faces several challenges. Therefore, new NAND flash technologies have been explored to provide larger capacity with low cost. Among these new technologies, the 3-D charge-trap flash is regarded as one of the most promising candidates. The 3-D charge-trap flash is composed of several gate-stack layers and vertical cylindrical channels to provide high-density and low cell-to-cell interference. Owing to the cylindrical geometry of vertical channels, the access performance of each page in one block is distinctive, and this situation is exacerbated in the 3-D charge-trap flash with the fast-growing number of gate-stack layers. In this paper, a progressive performance boosting strategy is proposed to boost the performance of 3-D charge-trap flash by utilizing its asymmetric page access speed feature. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the access performance of 3-D charge-trap flash.

This paper presents the design of dual-port subarray modularization integrating a three-port circulator, realized by using substrate integrated waveguide (SIW) technology, and a subarray of antenna elements for dual uplink and downlink beamforming. In particular, a $2\times2$ element module is implemented and fabricated on a standard printed circuit board substrate to demonstrate its radiation characteristics and operational mechanism. In this design, the SIW structure is used to reduce the radiation from microstrip lines at millimeter-wave frequencies and avoid contaminating the radiation patterns of subarrays. Greater than 5 dBi suppression has been achieved for good compatibility with the integration of radio frequency devices. The measured results show that the subarray modularization improves the insertion loss and results in an excellent isolation for independent transmitting and receiving beamforming network implementation. Numerical and experimental results are shown to verify the performance of these designs.

Mobile-phone based visible light communication (VLC) is an attractive method for optical wireless communication. However, the data rate is typically limited by the complementary metal-oxide-semiconductor image sensor frame rate and the processing time gap in the rolling shutter mode operation. Here, we propose and demonstrate a packet-reconstruction scheme, known as beacon jointed rolling shutter pattern scheme. The mobile-phone based VLC data rate can be increased to a record 10.32 kb/s. The implementation algorithm is discussed; and the bit-error-rate experimental evaluations at different transmission distances and horizontal offsets are performed.

Junctionless devices exhibit favorable $I_{{\rm on}}/I_{{\rm off}}$ and SS in high-mobility Ge channels owing to the elimination of junction leakage. With channel doping of 5 × 1018 cm−3, the fin width of 27 nm and the gate length of 250 nm, our gate-all-around device has the $I_{{\rm on}}/I_{{\rm off}}$ of 1 × 106, the SS of 95 mV/dec, and the $I_{{\rm on}}$ of 275 μA/μm. The drain current reaches 390 μA/μm for the device with channel doping of 8 × 1019 cm−3, and the fin width of 9 nm. The junctionless devices show higher mobility in the large $V_{{\rm GS}} -V_{T}$ region than the inversion mode devices due to less dependence on surface roughness scattering. Junctionless devices also show increasing drive current at increasing temperatures due to the nature of impurity scattering.

Nonplanar In0.53Ga0.47As gate wrap around field-effect transistors (GWAFETs) with atomic-layer deposited high- k dielectric and metal gate have been demonstrated in this paper. By applying novel device structure and optimizing fabrication process, In0.53Ga0.47As GWAFETs exhibit significant performance improvements over planar MOSFETs on both current drive capability and electrostatics control. In0.53Ga0.47As GWAFETs with fin width ( W \(_{\mathrm {{fin}}}\) ) 40–200 nm have been fabricated. Devices with narrower W \(_{\mathrm {{fin}}}\) exhibit higher drive current, transconductance, and better short channel effect control, which demonstrates the scalability of nonplanar In0.53Ga0.47As GWAFETs. Subthreshold swing of 80 mV/decade and drain-induced barrier lowering of 20 mV/V have been achieved by 40-nm W \(_{\mathrm {{fin}}}\) and 140-nm L \(_{{g}}\) In0.53Ga0.47As GWAFETs.

The Ge p-MOSFETs on (110) substrates using two-step implantation and NiGe contacts have been demonstrated. The record peak mobility of 528 ${\rm cm}^{2}/{\rm V}\cdot{\rm s}$ of the (110) Ge device is measured by the spilt $C{-}V$ method and can be further enhanced by proper stress. Ge p-FETs on (110) substrates have lower mobility enhancement than (100) devices under compressive strain along the channel. The peak mobility decreases with decreasing temperature due to impurity scattering. The larger density of interface states causes the larger threshold voltage shift from the room temperature to 100 K as compared with Si MOSFETs.

Notable improvements in the HfO2/In0.53 Ga0.47As gate stack have been achieved by a post- HfO2 fluorine plasma treatment, including excellent interface quality of low equivalent oxide thickness HfO2 (1.4 nm) directly on In0.53Ga0.47As without using an interface passivation layer, ~ 5× reduction in interface trap density from 2.8 ×1012 to 4.9 ×1011 cm-2eV-1, ~ 10× reduced border traps from 1.6 ×1019 to 1.6 ×1018 cm-3, and ~ 40% less charge-trapping centers. As a result, improved electrical performances have been obtained. Frequency dispersion in capacitance-voltage characteristics has been reduced. Subthreshold swing has been improved from 127 to 109 mV/dec. Effective channel mobility has been enhanced from 826 to 1067 cm2/Vs. An improved drive current of 123 mA/mm at Vd = 2.5 V and Vg - Vth = 2 V (5- μm channel length) has been also presented.

The conventional continuous scan and Delay-ID, lin methods of negative bias temperature instability characterization are not applicable for polycrystalline silicon thin-film transistors due to significant recovery effect and mobility degradation, respectively. An improved on-the-fly (OTF) method is proposed to simultaneously extract the threshold voltage shift and mobility degradation. In addition, the improved OTF method is more accurate than the continuous scan due to less recovery effect. The exponents of reaction-diffusion mechanism can be clearly determined using the new method.

This paper presents a new classifier called total margin-based adaptive fuzzy support vector machines (TAF-SVM) that deals with several problems that may occur in support vector machines (SVMs) when applied to the face recognition. The proposed TAF-SVM not only solves the overfitting problem resulted from the outlier with the approach of fuzzification of the penalty, but also corrects the skew of the optimal separating hyperplane due to the very imbalanced data sets by using different cost algorithm. In addition, by introducing the total margin algorithm to replace the conventional soft margin algorithm, a lower generalization error bound can be obtained. Those three functions are embodied into the traditional SVM so that the TAF-SVM is proposed and reformulated in both linear and nonlinear cases. By using two databases, the Chung Yuan Christian University (CYCU) multiview and the facial recognition technology (FERET) face databases, and using the kernel Fisher's discriminant analysis (KFDA) algorithm to extract discriminating face features, experimental results show that the proposed TAF-SVM is superior to SVM in terms of the face-recognition accuracy. The results also indicate that the proposed TAF-SVM can achieve smaller error variances than SVM over a number of tests such that better recognition stability can be obtained.

In the routine analysis of cephalometry, the orthodontist usually needs to manually draw the tracing paper with the help of the view box, and then some cephalometric measurements are performed to evaluate growth aspects of the skull and the effects of treatment. Due to the varied display quality and clinical training, many orthodontists rely heavily on the view box rather than the computer monitor for cephalometry. Without the appropriate and affordable digital imaging devices, the computerized analysis for cephalometry is hard to apply in practice. In this paper, a novel design of an intelligent view box that combines an X-ray film view box, a touch panel, and analysis software is proposed. It is designed for acquiring both the landmarks and feature curves of the cephalogram for the automated cephalometric system use. There are two merits of the proposed system. One is that the relationship between the label and position for manually defined landmarks may be automatically corrected, and the other is that the manual drawing process may be automatically followed and guided based on the cephalogram. In addition, the proposed system also includes an image manipulation system. Thus, both the landmarks and feature curves may be automatically and correctly overlaid on the cephalogram for further assessment. From the experimental results, the repeated repositioning of the pen in ten times only produces a standard deviation not more than 0.5 mm in x and y directions. The spatial resolution for the proposed intelligent view box system is about 164 pixels/inch. It is demonstrated to be very useful in the clinics for the automated cephalometric analysis.

High-energy extremely ultraviolet (EUV)-induced Ge MOSFETs degradation is investigated. The degradation of threshold voltage, subthreshold swing (SS), and channel mobility is attributed to the generation of interface traps and oxide fixed charges. Much more severe degradation of SS and VT on n-FETs compared to p-FETs suggests that more interface defects in the upper half of Ge bandgap are generated by EUV radiation than in the lower half bandgap. The increase of interface trap is responsible for the mobility degradation of n-FETs due to Coulomb scattering.

The effects of incorporating a thin silicon layer into a SiO2-based resistive-switching random access memory are presented. An improved performance, including a lower electroforming voltage and a more stable device current in the high-resistance programmed state, has been achieved by physical vapor deposition of a thin silicon layer onto the sidewall region of the device. Tristate pulse endurance performance over 106 cycles has been demonstrated. The programmed data show immunity to read disturb testing at 1 V and can be sustained up to 150°C thermal exposure. It is concluded that the improved performance is due to formation of a more robust and more uniform conducting filament. As a result of this advantage, stable tristate programming can be realized in the SiO2-based resistive memory device.

We have studied channel thickness dependence of InGaAs quantum-well field-effect transistors (QWFETs) with high-κ gate dielectrics. Device performances of ultrathin 5- and 10-nm-channel In0.7Ga0.3As QWFETs with gate length down to sub-50-nm regime have been investigated. Thinning down the channel improves subthreshold characteristics and reduces the short-channel effect. The 5-nm In0.7Ga0.3As channel (Lg = 40 nm) devices exhibit a reduced subthreshold swing (SS) of around 100 mV/dec and drain-induced barrier lowering (DIBL) of 128 mV/V compared to 10-nm In0.7Ga0.3As channel devices (SS of ~ 140 mV/dec and DIBL of ~ 275 mV/V). However, the drawback for thinner channel devices is that the effective channel mobility also decreases. At inversion charge density of 3 ×1012/cm2, 10-nm In0.7Ga0.3As channel devices exhibit mobility of 1860 cm2/V·s versus mobility of 1460 cm2/V·s for 5-nm In0.7Ga0.3As channel devices.

Sub-50-nm In0.7Ga0.3As MOSFETs with high-k dielectric Al2O3 have been demonstrated and investigated. The device performance of buried-channel In0.7Ga0.3As MOSFETs with various barrier layer materials (i.e., InP and InAlAs) has been analyzed and compared to that of devices without a barrier layer. The 40-nm-gate-length In0.7Ga0.3 As MOSFETs with InP/InAlAs barrier exhibit a subthreshold swing of 130 mV/dec, a drain-induced barrier lowering of 174 mV/V, and an extrinsic transconductance of 570 mS/mm at Vds = 1 V. Scaling behaviors of buried-channel In0.7Ga0.3As MOSFETs with and without a barrier layer material have also been analyzed.

This paper presents a new method for the implementation of an NTSC digital video decoder. This new fully digital architecture uses a phase-locked loop to compensate the unstable video source and an adaptive comb filter to improve the quality of Y/C separation. Simulation results show that it can successfully combat a sinusoidal timing variation of /spl plusmn/2 /spl mu/s for horizontal line lengths within one frame. It can also lock to a 3.58 MHz color subcarrier with frequency variation up to /spl plusmn/500 Hz.

Notable improvements in the HfO2/In0.53 Ga0.47As gate stack have been achieved by a post- HfO2 fluorine plasma treatment, including excellent interface quality of low-equivalent-oxide-thickness HfO2 (1.4 nm) directly on In0.53Ga0.47As with no interface passivation layer, over five-times reduction in interface trap density from 2.8 × 1012 to 4.9 × 1011 cm-2·eV-1, improved subthreshold swing from 127 to 109 mV/dec, and reduced Id-Vg hysteresis in pulsed Id-Vg measurement. Consequently, improved electrical performances have been achieved in 29% higher effective channel mobility and 29% higher drive current.

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is ~107 s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration.

Charge storage characteristics of a hafnium oxynitride (HfON) charge-trapping layer prepared by atomic layer deposition in a metal-Al2O3-HfON-SiO2-Si (MAHNOS) structure are investigated. We found that an ultrathin HfON (~2.5 nm) embedded in MAHNOS has large memory window (~7.5 V at Vg = ±15 V), sufficient erase speed (Δ VFB = 4 V at -16 V/1 ms), and satisfactory data retention. From the relation of erase transient current density (J) versus tunnel oxide e-field (ETUN), we also found that the erase mechanism of MAHNOS depends on electron detrapping from HfON to Si substrates. However, MAHNOS embedding with a thicker HfON shows a poor data retention due to the increase of crystallization of the trapping layer.

Single-crystalline Ge p-channel thin-film transistors with Schottky-barrier source/drain (S/D) on flexible polyimide substrates are fabricated by a simple low-temperature process ( ? 250°C), which preserves the high mobility of Ge channel. Adhesive wafer bonding and Smart-Cut techniques were utilized to transfer the single-crystalline Ge thin film onto polyimide substrates. The Schottky-barrier S/D is formed by using Pt/n-Ge contact, showing a low hole barrier height. The device has a linear hole mobility of ~ 170 cm2·V-1·s-1 and a saturation current of ~ 1.6 ?A/?m at Vd = - 1.5 V for the channel length and width of 15 and 280 ?m, respectively.

The dynamic stress switching of p-channel polycrystalline-silicon (poly-Si) thin-film transistors from full depletion to accumulation bias creates the high electric field near source/drain (S/D) junctions due to the slow formation of the accumulated electrons at the SiO2/poly -Si interface. The high electric field causes impact ionization near the S/D, where the secondary electrons surmount the SiO2 barrier and are trapped near the interface. The channel region near the S/D is inverted to p-type by the trapped electrons, and the effective channel length is reduced. The drain current increases with the stress time, particularly for short-channel devices.