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Read-ahead schemes have been widely used in page cache to improve read performance of Linux systems. As the Android system inherits the Linux kernel, the traditional read-ahead scheme is directly transplanted to mobile devices. However, request sizes and page cache sizes on mobile devices are much smaller, which may degrade read-ahead efficiency and therefore hurt user experience. This article first observes that many pages pre-fetched by read-ahead are unused, which causes frequent page cache eviction. And these evict operations could induce extra access latency, especially when write-back is conducting. Then, this article proposes a new analysis model to characterize the factors that closely relate to the access latency. It is found that there exists a trade-off between read-ahead size and access latency. Finally, this article proposes two optimized read-ahead schemes to exploit this trade-off under different situations. Size-tuning scheme aims to find the proper maximum size of read-ahead according to the characteristics of mobile devices. While MobiRA scheme improves the read-ahead efficiency by dynamically tuning read-ahead size and stop-settings. Experimental results on real mobile devices show that the proposed schemes can increase the efficiency of read-ahead scheme and improve the overall performance of mobile devices.

3-D triple-level cell (3-D TLC) NAND flash has high storage density and capacity, but degrading data reliability due to high raw bit error rates induced by a certain number of program/erase cycles. To guarantee data reliability, low-density parity-check (LDPC) codes are selected as the error correction codes in modern flash memories because of strong error correction capability. However, directly adopting LDPC codes induces high decoding latency due to iterative updating of log-likelihood ratio (LLR) information in the decoding process. Increasing LLR information accuracy can greatly improve decoding performance. In this paper, we propose EMAL: using error modes aware LDPC codes for further enhancing the decoding performance of 3-D TLC NAND flash. We first obtain 3-D TLC error modes based on an FPGA testing platform, and then exploit the error modes to optimize LLR information and enable the decoding to converge at a high speed. The simulation results show that the decoding performance is significantly improved, resulting in reduced bit error rates and decoding latency.

By storing multibit per cell, multilevel cell (MLC) NAND flash memory achieves high storage capacity, but sacrificing data reliability. Error correction codes, such as Bose–Chaudhuri–Hocquenghem (BCH) codes, are widely used to ensure data reliability. However, high raw bit error rates induced by interference noises make BCH codes become insufficient to guarantee data reliability. Low-density parity-check (LDPC) codes are considered as the replacement due to the stronger error correction capability. Nevertheless, directly exploiting LDPC codes introduces a concern about decoding latency because of their iterative decoding in the soft decision process. To develop effective LDPC decoding algorithms, it is necessary to have a more profound understanding on flash failure patterns. This paper first observes the pair-bit errors (PBEs) characteristic of MLC NAND flash memory on a real field-programmable gate array testing platform, then proposes a PBE-aware LDPC (PAL) decoding scheme-based upon this observation, in which PBE provides the promotion information for LDPC decoding to reduce decoding latency. Simulation results show that the decoding latency can be reduced by up to 54%, compared with the conventional LDPC codes.

3D-multi-level cell (MLC) NAND flash memory adopts 3D stack technology and stores two bits per cell, leading to improved storage capacities, but sacrificing data reliability. Low-density parity-check (LDPC) codes showing strong error correction capability benefit from their soft decision decoding, which is widely exploited to guarantee data reliability. Nevertheless, adopting LDPC codes can introduce a concern about read performance, because their iterative soft-decision decoding requires Log-Likelihood Ratio (LLR) information, called soft decision information, by applying multi-sensing voltages. This process of obtaining LLR information leads to high sensing and transferring latencies, lowering down 3D-MLC read performance. In particular, when raw bit error rates (RBER) are much higher due to the long retention periods and program/erase (P/E) cycles, this problem becomes more serious. In this paper, we propose a RBER-aware multi-sensing scheme for reducing sensing and transferring latencies, and thus improving read performance. This proposed scheme exploits the variations of RBER in flash pages with the increase of retention time and P/E cycles to dynamically apply sensing voltages. Simulation results show that this scheme significantly decreases the number of required sensing voltages while maintaining LDPC error correction capability, enhancing 3D-MLC read performance.