Search

In this article, a novel p-GaN high-electron-mobility transistor (HEMT) with a built-in Schottky barrier diode (SBD) is proposed and investigated by TCAD simulation. The anode contact of the integrated SBD is isolated from the ohmic contact of the source electrode by a p-GaN isolation region. The cathode of the SBD is connected to the drain electrode. In the proposed Schottky barrier diode/HEMT (SB-HEMT), a channel under the p-GaN isolation region is turned on during forward conduction to further reduce the specific on-resistance ( $R_{{on},sp}$ ). With a minimum sacrifice on $R_{{on},sp}$ , the reverse on-state voltage, $V_{R-{on}}$ (at a current density of 50 mA/mm), for the SB-HEMT is reduced by 33% (from 2.43 to 1.62 V) when compared with a conventional HEMT (C-HEMT). Compared with the C-HEMT with a separate on-chip SBD (C-HEMT/SBD), the SB-HEMT shows much better trade-off between $V_{R-{on}}$ and $R_{{on},sp}$ . The total switching loss ( $E_{total}$ ) of the proposed SB-HEMT with resistive load is lower than that of the C-HEMT and is reduced by up to 21% when compared with that of the C-HEMT/SBD with different area ratio between the HEMT and SBD regions.

Conventional di/dt and dv / dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.

An accurate method for the evaluation of breakdown voltages (BVs) in the superjunction-like (SJ-like) power devices is presented. This brief investigates the conventional SJ (c-SJ), the insulator pillar SJ (I-SJ), and the high-permittivity ( $\text{H}{k}$ ) structures. Based on the numerical calculations of the electric field line (EFL) distribution, the electric field profiles along the EFLs can be accurately obtained. This ensures the accurate determination of the impact ionization integrals and BV. The technology computer-aided design (TCAD) simulations confirm the validity of the proposed method. The proposed method could be of great significance for the optimization of the specific ON-resistance ( ${R} _{ \text {ON,sp}}$ ) and could provide a better understanding of the SJ-like power devices.

A new lateral power metal-oxide-semiconductor field-effect transistor (MOSFET) with dual conduction paths and high- ${k}$ passivation is proposed. The high- ${k}$ passivation enables the dual conduction paths to realize the double reduced surface field (RESURF) action and facilitates the formation of an accumulation layer during forward conduction. The proposed device offers a 42% reduction in specific on-resistance ( ${R}_{{ON},{SP}}{)}$ when compared to a similar size baseline device with the same breakdown voltage (BV). The technology computer-aided design (TCAD) simulation results, based on a $0.5~\mu \text{m}$ bipolar-CMOS-DMOS (BCD) compatible process, show that the proposed device is able to provide a ${R}_{{ON},{SP}}$ as low as 0.28 $\text{m}\Omega \cdot $ cm2 with a BV of 92 V.

Conventional insulated gate bipolar transistor (IGBT) current sensing and protection techniques usually employ discrete sensors, such as lossy shunt resistors, and may involve accessing the high-voltage collector load of the IGBT. This would normally present difficulties for integration. This paper presents an IGBT gate driver IC with a collector current sensing circuit and an on-chip CPU for local data processing. This IC is prototyped using a TSMC 0.18 μm 40 V BCD Gen-2 process. The collector current sensing technique is based on the unique Miller plateau relationship between the gate current and collector current ( $I_{C}$ and $I_{G}$ ) for a particular gate resistance ( $R_{G}$ ). It allows a cycle-by-cycle measurement of IC during both turn- on and turn- off transients without any extra discrete components. The temperature variation is compensated internally by the on-chip CPU using polynomial curve fitting. This technique only monitors the low-voltage signal at the gate terminal, without the need to handle any high-voltage signal on the collector/load side. Measurements using a double pulse test setup show an accuracy of ±0.5 A over the current ranges of 1–30 A for turn- on and 1–50 A for turn- off from 25 to 75 °C.