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To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically, Comment: 12 pages, 16 figures, 4 tables, 49 references. Submitted to IEEE TAS on Nov. 10, 2022

We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with $T_c$=15 K or of an in-situ deposited NbN/Nb bilayer, replacing a 200-nm Nb layer M6 in the standard SFQ5ee process with nine superconducting layers. Nb ground planes were preserved to maintain a high level of interlayer shielding and low intralayer mutual coupling. A two-step patterning of the top Nb and the bottom NbN layers of the NbN/Nb bilayer allows to create inductors in a very wide range of linear inductance values, from low values ~ 0.4 pH/$\mu$m typical for Nb geometrical inductors to ~ 35 pH/$\mu$m typical to thin-film kinetic inductors. Mutual inductance of NbN and Nb inductors, of NbN inductors, and of bilayer inductors is the same as between two Nb inductors with the same geometry and placement between the ground planes, i.e., mutual inductance does not depend on superconducting properties of the signal traces in the studied range of linewidths. We measured magnetic field penetration depth and kinetic inductance of NbN films with thickness t=200 nm to be $\lambda$ = 491+/-5 nm and 1.51 pH/sq, and 2.06 pH/sq at t=150 nm. The kinetic inductance was found to be larger than that expected for superconductors with short mean free path, indicating a reduction in the superfluid density, likely due to carrier localization effects. Kinetic inductance associated with right-angled bends of the NbN inductors is negligible at linewidths $w, Comment: 11 pages, 9 figures, 4 tables, 60 references

Future astrophysics missions such as the Lynx X-ray Microcalorimeter will comprise a very large array of X-ray microcalorimeters with greater than 100 000 pixels. One of the major challenges associated with the realization of large format arrays is the fabrication of high-density, high-yield, superconducting wiring between the pixels of the array. An attractive way to overcome this challenge is to use buried layers of multilayer wiring. Here we report on the fabrication of prototype arrays of magnetically coupled microcalorimeters (MMCs) using multiple niobium layers of buried wiring. In order to successfully scale MMCs to large arrays, so that the stray inductance of the wiring is sufficiently low and the sensor meander coil inductance is sufficiently high, the meander coil pitch is decreased. We have investigated linewidths as narrow as 400 nm. Fabricated devices have demonstrated high critical currents of 30 mA for the narrowest pitch.

In superconductor electronics fabrication processes developed at MIT Lincoln Laboratory, Josephson junctions (JJs) are placed near the top of the stack composed of nine or ten superconducting layers. We discuss the effects of this placement and other processing factors on uniformity of JJ critical current across 200-mm wafers; specifically, nonuniformity of residual stress in Nb films, wafer bow and warpage caused by accumulated stress in the underlying dielectric and superconducting layers, and effects of accumulated topography caused by patterning and planarization of wiring layers. We describe the typical fabrication defects, focusing primarily on the peculiar defects caused by electrochemical corrosion of dissimilar metals. To increase the integration scale and enhance fabrication capabilities, we are developing a new process, titled SC1, in which Nb/Al/AlO x /Nb JJs are placed near the bottom of the layer stack, preceded only by two planarized layers: resistor layer and superconducting ground plane. Six planarized Nb wiring layers are placed above the JJs. This layer stack should simplify routing of data and clock in integrated circuits, and allow for improvements in uniformity of small JJs. The SC1 process has a 250-nm minimum feature size for inductors, three sheet resistance options for resistors, and two options for JJ critical current density: 100 and 200 μA/μm 2 . We present fabrication details and process optimization aimed at improving JJ uniformity, increasing circuit yield, and reducing occurrence of corrosion defects to below the 1 ppm level.

The ability to localize defects in order to understand failure mechanisms in complex superconducting electronics circuits, while operating at low temperature, does not yet exist. This work applies thermally-induced voltage alteration (TIVA), to a biased superconducting electronics (SCE) circuit at ambient temperature. TIVA is a commonly used, laser-based failure analysis technique developed for silicon-based microelectronics. The non-operational circuit consisted of an arithmetic logic unit (ALU) in a high-frequency test bed designed at HYPRES and fabricated by MIT Lincoln Laboratory using their SFQ5ee process. Localized TIVA signals were correlated with reflected light images at the surface, and these sites were further investigated by scanning electron microscopy imaging of focused ion-beam cross-sections. The areas investigated, where prominent TIVA signals were observed, showed seams in the Nb wiring layers at contacts to Josephson junctions or inductors and/or disrupted junction morphologies. These results suggest that the TIVA technique can be used at ambient temperature to diagnose fabrication defects that may cause low temperature circuit failure.

We investigated current–voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities J c in order to extract their basic parameters and statistical characteristics for JJ modeling in superconducting integrated circuits as well as to assess their potential for future technology nodes. Nb/AlO x -Al/Nb junctions with diameters from 0.5 to 6 μm were fabricated using a fully planarized process with Mo or MoN x thin-film shunt resistors with sheet resistance R sq = 2 Ω/sq and R sq = 6 Ω/sq, respectively. We used our current standard MIT Lincoln Laboratory process node SFQ5ee to fabricate JJs with J c = 0.1 mA/μm2 and our new process node SFQ5hs (where “hs” stands for high speed) to make JJs with J c = 0.2 mA/μm 2 and higher current densities up to about 1 mA/μm2. Using LRC resonance features on the I–V characteristics of shunted JJs, we extract the inductance associated with Mo shunt resistors of 1.4 pH/sq. The main part of this inductance, about 1.1 pH/sq, is the inductance of the 40-nm Mo resistor film, while the geometrical inductance of superconducting Nb wiring contributes the rest. We attribute this large inductance to “kinetic” inductance arising from the complex conductivity of a thin normal-metal film in an electromagnetic field with angular frequency $\boldsymbol{\omega },$ ${{\mathbf \sigma }}(\boldsymbol{\omega }) = {\boldsymbol{\sigma }_0}/({1 + \boldsymbol{i\omega \tau }})$ , where ${{{\mathbf \sigma }}_0}$ is the static conductivity and $\boldsymbol{\tau }$ the electron scattering time. Using a resonance in a large-area unshunted high- J c junction excited by a resistively coupled small-area shunted JJ, we extract the Josephson plasma frequency and specific capacitance of high- J c junctions in 0.1–1 mA/μm2 J c range. We also present data on J c targeting and JJ critical current spreads. We discuss the potential of using 0.2-mA/μm2 JJs in very large scale integration single flux quantum circuits and 0.5-mA/μm2 JJs in high-density integrated circuits without shunt resistors.

A focused ion beam was used to obtain cross-sectional specimens from both magnetic multilayer and Nb/Al-AlOx/Nb Josephson junction devices for characterization by scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDX). Automated multivariate statistical analysis of the EDX spectral images produced chemically unique component images of individual layers within the multilayer structures. STEM imaging elucidated distinct variations in film morphology, interface quality, and/or etch artifacts that could be correlated to magnetic and/or electrical properties measured on the same devices.

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90-degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities > 10^6 Josephson junctions per cm^2 are discussed., 5 pages, 7 figures, 31 references. Presented at Applied Superconductivity Conference, ASC 2014, Charlotte, NC, USA, August 10-15, 2014

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO$_2$ interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, $I_c$, normal-state conductance, $G_N$, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, $J_c$, from 10 kA/$cm^2$ to 50 kA/$cm^2$ where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The $G_N$ and $I_c$ spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. $I_c$ and $G_N$ spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > $10^6$ JJ/$cm^2$ and 193-nm photolithography for JJ definition are discussed.

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 {\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of m{\Omega}-range resistors., Comment: 10 pages, 12 figures, 1 table, 27 references. The paper was presented on September 8, 2015 at the 12th European Conference on Applied Superconductivity, EUCAS 2015, 6-10 September 2015, Lyon, France, IEEE Transaction on Applied Superconductivity, 2016