Search

Computing-in-memory (CIM) based on SRAM is a promising approach to achieving energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices; however, existing SRAM-CIM chips support only DNN inference. The flow of training data requires that CIM arrays perform convolutional computation using transposed weight matrices. This article presents a two-way transpose (TWT) multiply cell with high resistance to process variation and a novel read scheme that uses input-aware zone prediction of maximum partial MAC values to enhance the signal margin for robust readout. A 28-nm 64-kb TWT CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved ${T_{AC}}$ of 3.8-21 ns and energy efficiency of 7-61.1 TOPS/W in performing MAC operations using 2-8-b inputs, 4-8-b weights, and 10-20-b outputs.

Physically unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with a wide range of applications in the Internet of Things (IoT). In recent years, novel PUF techniques based on resistive switching mechanism in various emerging nonvolatile memories have demonstrated superior performance on reliability and integration density. In this work, a resistive random access memory (RRAM)-based PUF chip with 8-kb capacity is developed. Two operation modes, namely differential mode and median mode, are embedded on chip. To implement these modes, a current sampling-based sense amplifier is designed to distinguish the current values of the PUF cells and the reference cell. In addition, a split-resistance scheme is proposed to enhance the PUF’s reliability significantly. The experiment results show that the differential PUF exhibits excellent performance with native bit error rate (N-BER) below 6 $\times $ 10−6 and inter-Hamming distance (inter-HD) of 49.99%. In the meanwhile, the reconfigurability of PUF challenge-response pairs (CRPs) is demonstrated with 49.77% and 47.29% reconfigure-Hamming distance (reconfigure-HD) in the median mode and the differential mode, respectively.

Millimeter wave (mmWave) provides extremely high throughput owing to their high bandwidth utilization over higher frequencies. To compensate for the severe loss and attenuation, beamforming training is used to determine the optimal beam direction and thereby improve directional transmission power. However, the training overhead will be significantly increased with narrower beams, particularly under conventional exhaustive schemes. Therefore, we propose a learning-based adjustable beam number training (LABNT) scheme to intelligently and flexibly select beam training candidates considering different user mobility and hybrid line-of-sight (LOS) and non-line-of-sight (NLOS) scenarios. In LABNT, several deep learning networks are parallelly constructed and connected to a reinforcement learning network to determine training candidates dynamically based on performance rewards. A novel enhanced feature selection method, that is, uniformly distributed mutual information, is developed based on the correlation of historical results to select the beam inputs for each deep learning network. In simulations, the proposed LABNT outperforms other existing schemes in terms of beam alignment accuracy, training latency, and system throughput. Moreover, following the IEEE 802.11ad/ay protocols, we implement realistic mmWave beamforming training on a programmable hardware platform with integrated 60 GHz wireless-gigabit (WiGig) transceiver devices. The experimental results on the WiGig platform demonstrate that the proposed LABNT scheme can achieve real-time performance with approximately Gbps transmission throughput and millisecond-level training overhead.

Computing-in-memory (CIM) based on embedded nonvolatile memory is a promising candidate for energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices. However, circuit design for NVM-based CIM (nvCIM) imposes a number of challenges, including an area-latency-energy tradeoff for multibit MAC operations, pattern-dependent degradation in signal margin, and small read margin. To overcome these challenges, this article proposes the following: 1) a serial-input non-weighted product (SINWP) structure; 2) a down-scaling weighted current translator (DSWCT) and positive–negative current-subtractor (PN-ISUB); 3) a current-aware bitline clamper (CABLC) scheme; and 4) a triple-margin small-offset current-mode sense amplifier (TMCSA). A 55-nm 1-Mb ReRAM-CIM macro was fabricated to demonstrate the MAC operation of 2-b-input, 3-b-weight with 4-b-out. This nvCIM macro achieved $T_{\text {MAC}}= 14.6$ ns at 4-b-out with peak energy efficiency of 53.17 TOPS/W.