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The total performance of low-k/Cu interconnects featuring short turnaround-time (TAT) silylated scalable porous silica (Po-SiO, k = 2.1) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, a 140-nm-pitch dual-damascene structure is successfully achieved. The wiring capacitance showed 10% reduction, compared to the conventional porous SiOC (ULK, k = 2.65). Sufficient interconnect reliability and packaging characteristics for the circuit-under-pad structure are also obtained. The predicted circuit performance was 8% higher than ULK in the 32-nm node.

A low oxygen content (LOC) CuAl alloy with no barrier metal (Ta) oxidation was obtained using an oxygen absorption process based on metallurgical thermodynamic principles. LOC CuAl dual damascene interconnects (DDIs) were successfully implemented into 45-nm-node LSIs with 140-nm-pitched lines and 70-nm-diameter (phi) vias. An oxygen absorber of very thin Al film, which was deposited on an electrochemically deposited (ECD) Cu film, captured the oxygen atoms in the ECD Cu due to its larger negative change in the standard Gibbs-free energy of oxidation than in the Cu and the barrier (Ta), preventing the Ta barrier from oxidizing during high-temperature annealing. The high-quality Cu/barrier interface in the LOC CuAl DDIs remarkably improved the via reliability against stress-induced voiding and electromigration. No reliability degradation of the 70-nm-phi vias was observed in the 45-nm-node LOC CuAl DDIs, while keeping the scalability from the 65-nm-node generation.

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant (keff) of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film (k = 2.5) is stacked directly on an oxygen (O)-rich porous SiOCH (k = 2.7) film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an Ar/N2 /CF4 /O2 gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS-SiOCH prevent the Si-CHx bonds from oxidation during O2-plasma ashing, suppressing the C-de- pleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film (k=2.6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid (k=2.9) or porous (k=2.6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O2 plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multi-hard-mask process for the DD structure in porous SiOCH film with no exposure to O 2-ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.

The plasma-etching technology presented in this paper is for fabricating highly reliable Cu dual damascene interconnects (DDI) with organic low-k film through modification of the in situ etched surface during low-k etching. Nitrogen-based plasma with oxygen and high-molecular-weight fluorocarbon gas (C>2) chemically modifies the sidewall surface of the etched low-k film, changing it into the carbon nitride with fluorocarbon-polymer passivation from the etching gas. After wet cleaning, the fluorocarbon-polymer is removed selectively, leaving a carbon nitride modified layer (CNL) on the sidewall. The CNL has been found to suppress Cu diffusion into the low-k film. A stacked barrier structure of conventional barrier metal and CNL is expected to have high tolerance to Cu diffusion. Combining a dual-hard-mask etching sequence with the CNL modification, Cu DDIs with organic low-k film were fabricated with high yield.