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This article presents and analyzes a wide-locking range divide-by-5 injection-locked frequency divider (ILFD) manufactured in the TSMC 0.18- $\mu \text{m}$ processes. The ILFD uses the balanced injection method and uses the pure harmonic mixing approach at low injection power, and it is designed with an RLC dual-resonance resonator. The harmonic mixer relies on the self-generated second harmonic, which increases with injection power. Because of no narrowband filter as used in the linear mixer counterpart, the divide-by-5 ILFD uses a wideband design method. In addition, the ILFD enhances the divide-by-5 locking range via the overlapped dual-band locking ranges as verified by both experiment and simulation. At the drain–source bias ${V} _{\text{DD}}$ of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-5 ILFD is 3.6 GHz, from the incident frequency 13.0–16.6 GHz with the percentage 24.3%. The core power consumption is 4.09 mW, and the die area is $1.02\times0.93$ mm2.

This article designs and analyzes LC injection-locked frequency dividers (ILFDs) using dual-resonance LC resonator. The ILFD consists of two single-resonance LC -tank capacitive cross-coupled sub-ILFDs operating at 3.7 and 5.1 GHz, respectively, and the two sub-ILFDs are coupled by the electric field through a pair of metal–insulator–metal (MIM) capacitors. The die area in the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18- $\mu \text{m}$ CMOS is $0.65\times1.023$ mm2. By controlling the gate voltages of the switching transistors, the ILFD has three different operational modes—high-band dominant mode, low-band dominant mode, and concurrent oscillation mode. Overlapped locking range is demonstrated for the first time in the designed electric-field coupling resonator ILFD. Non-overlapped locking range is found for the ILFD manifesting an effect of the dual-resonance resonator.

This article designs and analyzes wide locking range (LR) high even-modulus LC -tank injection-locked frequency dividers (ILFDs) with current-reused topologies. The current-reused LC ILFD uses two stacked LC sub-ILFDs sharing the same dc current. The current-reused ILFD becomes a divide-by-4 ( $\div 4$ ) ILFD, when both sub-ILFDs are used $\div 2$ ILFDs, and it is used as a divide-by-8 ( $\div 8$ ) ILFD when one sub-ILFD is used a $\div 4$ ILFD. Both sub-ILFDs use nMOSFETs as linear injection mixers for high conversion gain. For the $\div 8$ LC ILFD designed in the TSMC 0.18- $\mu \text{m}$ CMOS process, the circuit uses one high-frequency $\div 4$ sub-ILFD and one low-frequency $\div 2$ sub-ILFD, at the supply of 1.6 V, and at the incident power of 0 dBm, the LR is 4 GHz (38.835%), from the incident frequency 8.3 to 12.3 GHz. The $\div 8$ ILFD core power consumption is 13.98 mW, and the die size is $1.2 \times 1.2$ mm2. Both the $\div 8$ LC ILFD and the $\div 4$ sub-ILFD have nonoverlapped and overlapped LRs, which are due to a dual-resonance resonator used in the varactor-free n-core sub-ILFD. The LC dual-resonance resonator is due to parasitic capacitors in active FETs and on-chip spiral inductors and inductive elements, and it is used to get wide overlapped LR. Two $\div 4$ LC ILFDs inherent in the designed circuit are also studied.

Distributed LC resonator and resistively distributed resonator belong to the same technique used to extend the locking range of injection-locked frequency divider (ILFD). ILFD using the former resonator often has one locking range, and extension of locking range is attributed to oscillation frequency increment. This paper measures and analyzes the input sensitivity of a CMOS ILFD with a resistively distributed resonator and with the divide-by-3 and divide-by-2 functions, and the input sensitivity shows a wide single-band locking range. The fabricated 0.18- $\mu \text{m}$ CMOS ILFD is made of a pair of cross-coupled n-type transistors, two direct-injection MOSFETs, and a resistively dual-resonance resonator. The wide single-band locking range of the designed ILFD is owing to the overlapped locking ranges, and it is verified by the smooth tuning range without forbidden region and nonoverlapped locking ranges measured on the same chip with the unbalanced injection structure. The frequency tuning is obtained with large tank resistance, which also reduces the frequency tuning hysteresis effect.

A wide-locking range divide-by- $3~LC$ injection-locked frequency divider (ILFD) is proposed and implemented in the TSMC 0.18- $\mu \text{m}$ 1P6M CMOS process. The divide-by-3 ILFD uses a cross-coupled nMOS pair, an injection MOSFET pair, and a sixth-order $RLC$ resonator. The divide-by-3 ILFD has three oscillation frequency bands and three locking ranges. At the drain-source bias $V_{\mathbf {DD}}$ of 0.9 V and at the incident power of 0 dBm, by switching a varactor bias, the high-band, middle-band, and low-band locking ranges of the ILFD are, respectively, given by 3.47 GHz (33.87%) from 8.51 to 11.98 GHz, 3.72 GHz (54.86%) from 4.92 to 8.64 GHz, and 1.05 GHz (19.76%) from 4.88 to 5.93 GHz. The operation range is 7.1 GHz (84.2%) from 4.88 to 11.98 GHz. The ILFD-core power consumption is 6.759 mW. A wider locking range of 4.43 GHz (67.07%) from 4.39 to 8.82 GHz is obtained by overlapping the three locking ranges at a fixed bias condition. The die area is $0.991 \times 1.04$ mm2.

This letter presents a wide locking range divide-by-4 LC injection-locked frequency divider (ILFD) implemented in the TSMC 0.18- $\mu \text{m}$ 1P6M CMOS process. The single-stage divide-by-4 ILFD uses harmonic mixer and overlapped locking ranges to emulate a wide locking range. At the drain–source bias of 0.8 V, the ILFD-core power consumption is 7.09 mW. At the incident power of 0 dBm, the maximum locking range of the divide-by-4 ILFD is 6 GHz (37.5%) from 13 to 19 GHz. The ILFD comprises a capacitive cross-coupled nMOS pair and two shunt fourth-order RLC resonators. The die area is $1.008\times1.182$ mm $^{{{2}}}$ .

A novel divide-by-4 injection-locked frequency divider (ILFD) is proposed and was implemented in the TSMC $0.18~\mu \text{m}$ 1P6M CMOS process. Conventional harmonic mixer divide-by-4 ILFD has limited locking range, and this letter shows a wide locking range divide-by-4 ILFD designed with linear mixer technique. At the drain–source bias of 1 V and at the incident power of 0 dBm, the locking range is 3.9 GHz (36.28%) from 8.8 to 12.7 GHz at the power consumption of 3.61 mW. The free-running oscillation frequency is 2.6 GHz. The proposed ILFD is based on a cross-coupled voltage-controlled oscillator.

This paper proposes a high-performance CMOS voltage-controlled oscillator (VCO) with two subfrequency bands. The VCO consists of two cross-coupled VCOs coupled by a pair of mode-switched inductors. Two pairs of shunt varactors are used to switch high- and low-frequency bands. With the varactors as the mode switches, the odd mode VCO operates at the high frequency (C-band) and the even mode VCO operates at the low frequency (S-band). The proposed VCO has been implemented with the TSMC 0.18- $\mu $ m 1P6M CMOS technology and it can generate differential signals in the frequency range of 5.21–6.66 GHz (IEEE 802.11a) and 3.26–3.84 GHz (IEEE 802.16a) and it also has high output voltage swings at both low- and high-frequency bands. The die area of the dual-band VCO is 0.976 mm $\times 1.092$ mm. At the supply voltage of 0.75 V, the high(low)-band figure of merit is −190.5(−190.4) dBc/Hz.

Conventional harmonic mixer divide-by-3 ILFD has limited locking range. This letter shows a wide locking range ÷3 ILFD designed with the enhanced 2nd harmonic technique. The proposed ILFD is based on a cross-coupled voltage-controlled oscillator (VCO) and was implemented in the TSMC $0.18 \mu\ \!\!\text{m}$ 1P6M CMOS process. At the drain-source bias $V_\mathrm{DD}$ of 0.8 V and at the incident power of 0 dBm, the locking range is 4 GHz (50%), from the incident frequency 6 GHz to 10 GHz. The core power consumption is 7.72 mW and the die area is $0.939\times 0.885 \text{mm}^{2}$ .

A switching network exploiting the principle that the resultant phase noise of VCO will be reduced in proportion to 1/ $N$ , if $N$ oscillators are ideally coupled together. The VCO consists of two cross-coupled oscillators joining by a pair of mode-switched inductors. Two pairs of MOS transistors are used to switch high- and low-frequency bands. With even mode (low-band), the voltages across the resonators are in phase with equal amplitude and with odd mode (high-band), the voltages are 180 $^{\circ}$ out of phase with equal amplitude. When the tank's inductance reduces due to the switching to operate the circuit at the high-frequency band, the capacitance is the same as that at the low-band.

By exploiting the intrinsic multiple oscillation modes of LC resonator with cross-coupled transistor pair, a differential VCO is designed for multi-standard RF transceivers. The series resistance introduced by transistor switches has been omitted to improve the quality factor of resonator. It operates at the high-frequency series-resonant and low-frequency parallel-resonant mode via varactor switching bias. Both frequencies are not harmonically related. Accumulation-mode MOS varactor tuning changes the net impedance of LC-tank to shift the oscillations from one resonance mode to another.

A wide locking range CMOS LC-tank injection locked frequency divider (ILFD) is proposed and it uses a pre-amplifier stage in series with a post-injection mixer. The injection signal is fed to a pre-amplifier to enhance the injection signal at the post-mixer gate in the divide-by-2 ILFD. The gate of mixer is biased in sub-threshold to provide large output voltage. At the supply voltage of 0.85 V, tunable free-running low-frequency band from 3.23 to 3.59 GHz and high-band from 1.71 to 1.73 GHz are found. The low-/high-band locking range is (61.7%) from 2.8 to 5.3 GHz/(64.9%) from 5.1 $\sim$ 10.0 GHz.

This letter presents a low phase noise triple-band voltage-controlled oscillator (VCO). The designed circuit consists of a dual-resonance LC-tank VCO and a single-resonance LC-tank VCO. The two sub-VCOs are coupled via transformers and varactors. The net LC resonator has three main resonant frequencies selectable by controlling the bias of varactors. The proposed VCO has been fabricated with the TSMC 0.18 $\mu$ m 1P6M CMOS technology. The VCO can generate differential signals in the frequency range of 2.80–3.57, 7.43–7.65, and 8.23–8.77 GHz with core power consumption of 3.3, 4, and 4.2 mW at the dc drain-source bias of 0.65 V, respectively. At 3.49, 7.53, and 8.52 GHz phase noises at 1 MHz offset are ${-}123.06$ dBc/GHz, ${-}119.62$ dBc/Hz, and ${-}118.34$ dBc/Hz, respectively. The die area of the triple-band VCO is 0.626 $\, \times \,$ 0.912 mm $^{2}$ .

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two p-core cross-coupled voltage-controlled oscillators (VCOs) using indirect back-gate coupling. In conventional direct-back coupling the resonator's voltage swing, tuning range, and quality factor are respectively limited by the forward-conducting back-gate junction cut-in voltage, diffusion capacitance and small dynamic resistance. To generate quadrature phase signals with strong coupling strength and large output swing, the proposed design uses pMOSFETs as buffers between the back-gate diode and LC tank to eliminate the drawback in existing back gate coupling QVCOs. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M technology. At the supply voltage of 0.8 V, the total power consumption is 4.4 mW. The free-running frequency of the QVCO is tuneable from 5.96 GHz to 6.60 GHz as the tuning voltage is varied from 0.0 V to 0.8 V. The measured phase noise at 1 MHz frequency offset is -120.5 dBc/Hz at the oscillation frequency of 6.59 GHz and the figure of merit (FOM) of the proposed QVCO is -190.4 dBc/Hz.

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) coupled via varactors. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm CMOS technology and the die area is 0.61 × 0.95 mm2. At the supply voltage of 1.2 V, the total power consumption is 3.7 mW. The free-running frequency of the QVCO is tunable from 3.86 GHz to 4.22 GHz as the tuning voltage is varied from 0.0 to 1.2 V. The measured phase noise at 1 MHz frequency offset is -123.42 dBc/Hz at the oscillation frequency of 3.94 GHz and the figure of merit (FOM) of the proposed QVCO is -190.38 dBc/Hz.

This letter studies the property of a divide-by-2 quadrature injection-locked frequency divider (QILFD) with dual-resonance resonator. The QILFD consists of a transformer-coupled quadrature voltage controlled oscillator and two NMOS injectors. The proposed QILFD has been implemented with the TSMC 0.18 μm CMOS technology and the core power consumption is 3.4 mW at the supply voltage of 0.75 V. At the input power of 0 dBm, the low-band and high-band divide-by-2 operation ranges are respectively from 6.3 GHz to 8.2 GHz and 8.1 GHz to 10.3 GHz. The high-frequency band tuning range of free-running QILFD can be measured after the power-on, and the low-frequency band tuning range of free-running QILFD can be measured only after the low-frequency band injection signal is injected to the QILFD.

A new low power wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.13 m CMOS process is presented. The push-push ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator with linear mixer to extend the locking range. The power consumption of the ILFD core is 2.05 mW. The divider's free-running frequency is tunable from 4.37 to 5.43 GHz by tuning the varactor's control bias, and at the incident power of 0 dBm the maximum locking range is 2.6 GHz (16.5%), from the incident frequency 14.5 to 17.1 GHz. The operation range is 5.1 GHz (35.1%), from 12.0 to 17.1 GHz.

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with two tail inductors. The two differential VCOs are coupled via two tail inductors to form a quadrature VCO. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm CMOS technology and the die area is 0.83 × 0.96 mm2. At the supply voltage of 1.45 V, the free-running frequency of the QVCO is tunable from 4.94 to 5.22 GHz as the tuning voltage is varied from 0.0 to 1.0 V. The total power consumption is 8.7 mW and the measured phase noise at 1 MHz frequency offset is -124.58 dBc/Hz at the oscillation frequency of 5.15 GHz and the figure of merit (FOM) of the proposed QVCO is -189.42 dBc/Hz.

An ultra-low voltage differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 ? m CMOS 1P8M process. The designed circuit topology is an nMOS-core cross-coupled LC-tank VCO, and a self-generated 2nd harmonic ac signal is coupled to the bodies of MOSFETs to enhance the VCO performance. At the supply voltage of 0.3 V, the output phase noise of the VCO is -116.88 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 3.579 GHz, and the figure of merit is -194.43 dBc/Hz. Total power consumption is 0.225 mW. Tuning range is about 240(770) MHz, from 3.39 to 3.63(4.16) GHz, while the control voltage was tuned from 0 V to 0.3(1.0) V.

A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 mum CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78-5.19 GHz and 12.19-12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are -117.16 dBc/Hz and -112.15 dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply.

Using the transformer coupling technique, this letter presents a new quadrature voltage-controlled oscillator (QVCO) with bottom series-coupled transistors. The proposed CMOS QVCO has been implemented with the TSMC 0.13 mum 1P8M CMOS process, and the die area is 1.03 times 0.914 mm2. At the supply voltage of 1.0 V, the total power consumption is 3.56 mW. The free-running frequency of the QVCO is tunable from 5.43 GHz to 5.92 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz frequency offset is -117.98 dBc/Hz at the oscillation frequency of 5.5 GHz and the figure of merit (FOM) of the proposed QVCO is -187.27 dBc/Hz.

This letter presents a new low power quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no DC voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.512 times 1.065 mm2. At the supply voltage of 1.1 V, the total power consumption is 2.545 mW. The free-running frequency of the QVCO is tunable from 4.38 to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1 MHz frequency offset is -120.8 dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is -189.61 dBc/Hz.

This letter presents an ultra-low voltage quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two low-voltage voltage-controlled oscillators (VCOs) with the body dc biased at the drain bias through a resistor. The superharmonic and back-gate coupling techniques are used to couple two differential VCOs to run in quadrature. The proposed CMOS QVCO has been implemented with the UMC 90 nm CMOS technology and the die area is 0.827 × 0.913 mm2. At the supply voltage of 0.22 V, the total power consumption is 0.33 mW. The free-running frequency of the QVCO is tunable from 3.42 to 3.60 GHz as the tuning voltage is varied from 0.0 to 0.3 V. The measured phase noise at 1 MHz offset is -112.97 dBc/Hz at the oscillation frequency of 3.55 GHz and the figure of merit (FOM) of the proposed QVCO is about -188.79 dBc/Hz.

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 mum CMOS 1P8M process. The designed circuit topology is an all nMOS LC-tank Clapp-VCO using a series-tuned resonator. At the supply voltage of 0.9 V, the output phase noise of the VCO is -110.5 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 18.78 GHz, and the figure of merit is -188.67 dBc/Hz. The core power consumption is 5.4 mW. Tuning range is about 3.43 GHz, from 18.79 to 22.22 GHz, while the control voltage was tuned from 0 to 1.3 V.

A new wide-locking range multi-modulus LC-tank injection locked frequency divider (ILFD) is proposed and was fabricated in a 0.18 mum CMOS process. The ILFD circuit is realized with a complementary MOS LC-tank oscillator and an injection composite composed of an inductor in series with an injection MOS. The two output terminals of the injection composite are connected to the resonator outputs. The ILFD can be used as a first-harmonic oscillator (ILO), even-modulo or odd-modulo oscillator depending upon the incident frequency of injection signal. At the supply voltage of 1.5 V, the free-running frequency is from 4.85 to 5.13 GHz, the current and power consumption of the divider without buffers are 2.78 and 4.17 mW, respectively. At the incident power of 0 dBm, the locking range in the divide-by-1(2, 3, 4) mode is from the incident frequency 3.72 to 8.69 (8.42 to 10.95, 13.66 to 16.03, 19.13 to 20.5) GHz.

This letter presents a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) divide-by-4 injection locked frequency divider (ILFD). The ILFD is based on a single-stage voltage-controlled oscillator with active-inductor, and was fabricated in the 0.35 mu m SiGe 3P3M BiCMOS technology. The divide-by-4 function is performed by injecting a signal to the base of the tail HBT. Measurement results show that when the supply voltage VDD is 3.1 V and the tuning voltage is tuned from 2.0 to 2.8 V, the divider free-running oscillation frequency is tunable from 2.12 to 2.76 GHz, and at the incident power of 0 dBm the operation range is about 1.15 GHz, from the incident frequency 8.55 to 9.7 GHz. The die area is 0.65 times 0.435 mm2.

A new injection-locked frequency divider (ILFD) using a standard 0.18 mum CMOS process is presented. The ILFD is based on a differential Colpitts voltage controlled oscillator (VCO) with a direct injection MOSFET for coupling an external signal to the resonators. The VCO is composed of two single-ended VCOs coupled with two transformers. Measurement results show that at the supply voltage of 1.4 V the divider's free-running frequency is tunable from 4.77 to 5.08 GHz, and the proposed circuit can function as a first harmonic injection-locked oscillator, divide-by-2, -3, and -4 frequency divider. At the incident power of 0 dBm the divide-by-2 operation range is from the incident frequency 7.7 to 11.5 GHz and the divide-by-4 operation range is from the incident frequency 18.9 to 20.2 GHz.

This letter presents a wide-locking range, body-injected, injection locked frequency divider (ILFD) with tunable active inductors (TAIs) and variable division ratio. The ILFD was fabricated in the 0.18 mum 1P6M CMOS technology, and it has the modulus of 2, 3, 4, and 5, and can be used as a first-harmonic injection-locked oscillator (ILO). The divide-by-3 function is performed by injecting differential a signal to the bodies of cross-coupled transistors in the VCO. At the supply voltage of 1.5 V, the free-running divider is tunable from 0.53 to 1.72 GHz. At the incident power of 0 dBm the operation range in the first-harmonic ILO is from the incident frequency 0.53 to 3.2 GHz. The operation range in the divide-by-3 (divide-by-2) mode is about 3.59 (4.13) GHz, from the incident frequency 1.55 to 5.14 (0.87 to 5.0) GHz.

This letter presents a new quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two first-harmonic injection-locked oscillators (ILOs). The outputs of one ILO are injected to the gates of the tail transistors on the other ILO and vice versa so as to force the two ILOs operate in quadrature. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.582 times 0.972 mm2. At the supply voltage of 1.0 V, the total power consumption is 8.0 mW. The free-running frequency of the QVCO is tunable from 5.31 GHz to 5.75 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz offset is -120.01 dBc/Hz at the oscillation frequency of 5.31 GHz and the figure of merit (FOM) of the proposed QVCO is about -185.48 dBc/Hz.

A new wide locking range injection-locked frequency divider (ILFD) using a standard 0.18-mum CMOS process is presented. The ILFD is based on a differential voltage controlled oscillator (VCO) with two embedded injection metal oxide semiconductor field effect transistors (MOSFETs) for coupling external signal to the resonators. The new VCO is composed of two single-ended VCOs coupled with cross-coupled MOSFETs and a transformer. Measurement results show that at the supply voltage of 1.5 V, the divider's free-running frequency is tunable from 5.85 to 6.17 GHz, and at the incident power of 0 dBm the locking range is about 7.1 GHz (65.4%), from the incident frequency 7.3 to 14.4 GHz. The ILFD has a record locking range percentage among published divide-by-2 .LC-tank ILFDs.

This letter proposes a wide locking range and low power complementary Colpitts injection-locked frequency divider (ILFD) employing a 3-D helical transformer. The proposed ILFD consists of two single-ended complementary Colpitts oscillators coupled by a 3-D transformer to form a differential oscillator. The aim of using the 3-D transformer is to reduce chip size. The divide-by-2 LC-tank ILFD is implemented by adding an injection nMOS between the differential outputs of the voltage controlled oscillator. The measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 4.24 to 4.8 GHz. At the incident power of 0 dBm, vtune=0.9 V, and V DD=1.5 V, the locking range is about 2.4 GHz (26.9%), from the incident frequency 7.7 to 10.1 GHz. The core power consumption is 3.9 mW. The die area is 0.548times 0.656 mm2.

This letter proposes a new wideband Colpitts injection locked frequency divider (ILFD) and describes the operation principle of the ILFD. The circuit consists of a differential CMOS LC-tank oscillator and a direct injection topology. The divide-by-two ILFD can provide wide locking range, and the measurement results show that at the supply voltage of 2.4 V, the tuning range of the free running ILFD is from 4.46 to 5.6 GHz, about 1.14 GHz, and the locking range of the ILFD is from 8.03 to 11.63 GHz, about 3.6 GHz, at the injection signal power of 0 dBm. The ILFD dissipates 19.92 mW at a supply voltage of 2.4 V and was fabricated in 1P6M 0.18 mum CMOS process. At the tuning voltage of 1.2 V, the measured phase noise of the free running ILFD is -110.8 dBc/Hz at 1 MHz offset frequency from 4.94 GHz and the phase noise of the locked ILFD is -135.4 dBc/Hz, while the input signal power is -4 dBm.

This letter proposes a wideband injection-locked frequency divider (ILFD) and describes the operation principle of the ILFD. The circuit is made of a differential CMOS LC-tank oscillator and is based on the direct injection topology. The wideband function is obtained by tuning the switch across the tank inductors. The divide-by-two ILFD can provide wide locking range and the measurement results show that at the supply voltage of 1.8 V, the dual-band divider free-running frequencies are from 1.77 to 2.17 GHz for the low-band mode, and from 2.59 to 3.2 GHz for the high-band mode. At the incident power of 0 dBm, the locking range is about 1.7 GHz from the incident frequency 3.31 to 5.01 GHz at low band and 4.06 GHz from 3.94 to 8.0 GHz at high-band mode. The circuit can be used as a single wideband ILFD.

This letter proposes a new wide band CMOS injection locked frequency divider (ILFD). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. A tuning circuit composed of inductors in series with a metal oxide semiconductor field effect transistor is used to extend the locking range. The divide-by-two ILFD can provide wide locking range and the measured results show that at the supply voltage of 1.8 V, the free-running frequency of the ILFD is operating from 0.92 to 3.6 GHz while the Vtune is tuned from 0 to 1.8 V. At the incident power of 0 dBm, this ILFD has a wide locking range from 1.15 to 7.4 GHz

This letter presents a low voltage quadrature divide-by-4 (divide4) injection-locked frequency divider (QILFD). The QILFD consists of a 1.8-GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are inserted into the quadrature outputs of the QVCO for signal injection. The low-voltage CMOS divide4 QILFD has been implemented with the TSMC 0.18-mum 1P6 M CMOS technology and the core power consumption is 3.12mW at the supply voltage of 1.2V. The free-running frequency of the QILFD is tunable from 1.73 to 1.99GHz, the measured phase noise of QILFD is -118dBc/Hz at 1-MHz offset from the free running frequency of 1.82GHz. At the input power of 0dBm, the total locking range is from 6.86 to 8.02GHz as the tuning voltage is varied from 0 to 1.2V. The phase noise of the locked output spectrum is lower than that of free running ring oscillator by 11dBc/Hz. The phase deviation of quadrature output is about 0.8deg

A 1.1-GHz voltage control oscillator (VCO) using a standard 0.18-mum CMOS 1P6M process is fabricated. The VCO was designed with dynamic threshold voltage metal-oxide-semiconductor field-effect transistors and extremely-low-voltage and low power operation is achieved using on-chip transformers in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. This VCO prototype is designed for a 0.34-V supply voltage while the output phase noise is -121.2dBc/Hz at 1-MHz offset frequency at the carrier frequency of 1.14GHz, the figure of merit is -192.0dB. The total power consumption is 103.7muW with the 0.34-V supply voltage. Tuning range is from 1.06 to 1.14GHz about 80MHz while the control voltage was tuned from 0 to 1.8V. The die area is 0.625times0.79mm2

This letter presents a new current reused LC-tank injection locked oscillator (ILO), which is implemented by using a standard TSMC 0.18-mum CMOS process. The ILO, used as a divide-by-two (divide2) divider, is consisted of two switching transistors stacked in series. The injection locking is performed by adding an injection nMOS between the differential outputs of the divider. The divider can operate with a lower power due to the reuse of dc current. The measurement results show that at the supply voltage of 1.5V, the divider free-running frequency is tunable from 2.11 to 2.42GHz, and at the incident power of 0dBm the locking range of the divider in the divide2 mode is about 0.9GHz (19.8%), from the incident frequency 4.1 to 5GHz. The core power consumption is 0.97mW

This letter describes circuit techniques for obtaining divide-by-four (divide4) frequency dividers (FDs) from CMOS ring-oscillator based injection locked frequency dividers (ILFDs). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. At the supply voltage of 1.8V and at the incident power of 0dBm, for a dual-band ILFD, the divide4 ILFD can provide a locking range of 6.3% from 5.39 to 6.12GHz at low band and 5.9% from 8.84 to 9.38GHz at high band when the dc bias of MOS switches Vinj changes from 0.7 to 1.1V

This letter presents a novel Hartley low phase noise differential CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18-mum 1P6M CMOS technology and adopts full PMOS to achieve a better phase noise performance. The VCO operates from 4.02 to 4.5GHz with 11.3% tuning range. The measured phase noise at 1-MHz offset is about -119dBc/Hz at 4.02GHz and 122dBc/Hz at 4.5GHz. The power consumption of the VCO core is 6.75mW

This letter presents an integrated direct-injection locked quadrature voltage controlled oscillator (VCO), consisted of a 5-GHz VCO integrated with injection locked LC frequency dividers for low-power quadrature generation. The circuit is implemented using a standard 0.18-mum CMOS process. The differential VCO is a full PMOS Colpitts oscillator, and the frequency divider is performed by adding an injection nMOS between the differential outputs of complementary cross-coupled np-core LC VCO. The measurement results show that at the supply voltage of 1.8-V, the master 5-GHz VCO is tunable from 4.73 to 5.74GHz, and the slave 2.5-GHz VCO is tunable from 2.36 to 2.87GHz. The measured phase noise of master VCO is -118.2dBc/Hz while the locked quadrature output phase noise is -124.4dBc/Hz at 1-MHz offset frequency, which is 6.2dB lower than the master VCO. The core power consumptions are 7.8 and 8.7mW at master and slave VCOs, respectively

This letter proposes 5-GHz low power differential Armstrong voltage controlled oscillators (VCOs) based on balanced topology. One designed VCO uses two single-ended Armstrong VCOs coupled to each other in parallel by balanced structure. The other current-reused VCO uses two single-ended Armstrong VCOs stacked in series. The former VCO oscillates from 4.96 to 5.34GHz and the power consumption is 3.9mW at 0.6-V supply voltage. The latter operates from 4.98 to 5.45GHz and dissipates 2.59mW at 1.8-V supply voltage. The measured phase noises are about -116.71dBc/Hz and -110.02dBc/Hz at 1-MHz offset frequency from 5.1-GHz band, respectively. The former and the latter VCO have an advantage of low power consumption and provide a good figure of merit of about -185dBc/Hz and -180dBc/Hz, respectively

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries.

Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data.

A novel low-voltage quadrature voltage-controlled oscillator (QVCO) with voltage feedback to the input gate of a switching amplifier is proposed and implemented using the standard TSMC 0.18-mum CMOS 1P6M process. The proposed circuit topology is made up of two low-voltage LC-tank VCOs, where the coupled QVCO is obtained using the transformer coupling technique. At the 0.7-V supply voltage, the output phase noise of the VCO is -124.9 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 2.4GHz, and the figure of merit is -185.35dBc/Hz. Total power consumption is 5.18 mW. Tuning range is about 135 MHz while the control voltage was tuned from 0 to 0.7V

This letter proposes a divide-by-four injection-locked frequency divider (ILFD) with the use of a subharmonic mixer and a divide-by-two frequency divider (D2FD). The D2FD circuit consists of a two-stage differential CMOS ring oscillator with n-MOS switches directly coupled to its differential outputs, the measured phase noise of the D2FD is -97 dBc/Hz at 1-MHz offset from the free running frequency of 1.08GHz. The low-voltage CMOS divide-by-four FD (D4FD) has been implemented with the UMC 0.18-mum 1P6M CMOS technology and the power consumption is 9 mW at the supply voltage of 1.2 V. At the input power of 0 dBm, the D4FD can function properly with about 330-MHz locking range from 4.15 to 4.48GHz

This letter proposes a wide locking range injection locked frequency divider (ILFD) and describes the operation principle of the ILFD. The circuit is made of a dual band two-stage differential complementary metal-oxide-semiconductor (CMOS) ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. The divide-by-two ILFD can provide wide locking range and the measurement results show that at the supply voltage of 1.8-V, the divider free-running frequencies are 1.36GHz and 2.3GHz, and at the incident power of 0dBm, the locking range is about 1.75GHz from the incident frequency 1.9GHz to 3.65GHz at low band and 2.55GHz from 2.95GHz to 5.5GHz at high band