Search

In many grid synchronization systems (GSSs), amplitude and phase estimation loops are dynamically coupled. It means that a change in the input voltage amplitude may result in spurious phase/frequency transients in the GSS output, and vice versa. This paper aims to explain the reason behind this coupling and present some guidelines to mitigate it. Several case studies are provided and numerical and experimental results are presented to make all this more clear.

This letter analyzes the impact of hybrid voltage- and power-based synchronization control on the transient stability of grid-forming (GFM) inverters. It is found that the added voltage-based synchronization loop exploits the phase angle difference to resist frequency deviation, whose function is similar to the damper winding of synchronous generators. By resembling the large-signal model of such hybrid synchronization control (HSC) to the power-angle swing equation, it is proved that the HSC brings higher damping to the system and thus, enhances the transient stability of GFM inverters. Further, a comparative study of two active power controllers, i.e., the droop controller with a low-pass filter and the proportional-integral (PI) controller, is given. It is revealed that the HSC with the droop controller equivalently decreases the active power reference, which leads to better transient stability behavior than that of using the PI controller. The theoretical findings are corroborated by experimental tests.

This article presents an adaptive notch filter (ANF) based efficient control algorithm for multifunctional grid connected solar photovoltaic (PV) powered electric vehicle (EV) charger to power the EV batteries and simultaneously improve the grid power quality. Furthermore, a multilevel topology is adopted for the grid-facing converter to improve output voltage quality. The ANF accurately estimates the fundamental EV current and grid voltage for generating pure sinusoidal reference current and synchronizing voltage template, respectively. The ANF-based voltage template estimator precisely estimates in-phase and in-quadrature synchronizing voltage templates compared to a phase-locked loop and second-order generalized integrator during nonideal grid voltage conditions. The charger is designed to operate in grid connected operation (GCO) and standalone operation (SO) to optimize the PV generation. In GCO, the charger provides grid current harmonic compensation and reactive power support to the grid. Furthermore, it offers backup power to the residential load during an emergency. The charger control algorithm also includes a grid synchronization technique based on phase error minimization to achieve a smooth and seamless transition from SO to GCO and vice versa. The effectiveness of the proposed control algorithm is validated in a 12.6-kVA off-board EV charger laboratory prototype. The obtained results verify the charger performance complies with IEEE 1547 standard.

This work presents the modelling fundamentals to study the dynamics of inverter-based resources (IBRs) in weak distribution grids and derive disturbance performance characteristics describing how they should behave under different conditions. More specifically, with respect to small-signal disturbances we study the possible voltage violations following frequency response from IBRs due to low system strength and also propose specific design requirements for IBR d-q current control to guarantee a stable response. In the context of large-signal disturbances, we highlight how active power-voltage control may not be effective due to a delay imposed by the physical features of the distribution network. Further, we mathematically discuss how IBR reactive power control could enhance its phase-locked loop stability. The proposed disturbance performance characteristics are then integrated into the IBR converter control via a novel voltage-priority reference generation strategy. Simulation results on a real Australian network show the efficacy of the proposed operational and control design requirements, and highlight possible unexpected active/reactive power interactions in weak distribution grids.

In single-phase voltage source inverters (VSI) under a weak grid, the frequency coupling, caused by the asymmetrical system structure, poses a challenge to system modeling and controller design. In this article, a frequency coupling suppression control strategy is presented, where all the frequency coupling components in the current reference are eliminated. As a result, the single-phase grid-tied inverter is directly modeled as a simple single-input single-output (SISO) admittance rather than a complicated multiple-input multiple-output (MIMO) admittance matrix. The SISO admittance model is simple, compact, and accurate, which facilitates design-oriented analysis. The admittance characteristic analysis shows that the Sym-PLL has a critical impact on the system stability under weak grid conditions. To improve the system stability, a prefilter-based impedance-shaping control strategy is proposed by mitigating the negative resistor behavior of the Sym-PLL. Finally, simulations and experimental results validate the effectiveness of the frequency-coupling suppression control strategy.

Speed estimation schemes based on the closed-loop synchronization (CLS) methods for speed-sensorless control of motor drives attract much popularity due to several advantages, e.g., easy implementation, high flexibility, and acceptable performance. However, most of the existing CLS-based estimation schemes may suffer from performance degradation during frequency ramps. Considering this, an attempt of the type-3 phase-locked loop (PLL)-based scheme is made. This solution, however, may adversely affect the system dynamics and stability margin. To address these issues, an open-loop synchronization (OLS) method is proposed for speed-sensorless control of induction motor drives in this paper. In the proposed scheme, the estimated speed is obtained according to the sinusoidal signals and their time-delay signals, rather than increasing the system order. With this, system dynamics and stability margin are maintained. In practice, the disturbance of DC offsets is of concern in induction motor drives. Thus, a closed-loop flux observer is adopted to guarantee the estimation performance under DC offsets. The performance of the proposed OLS scheme is investigated and compared with that of the CLS schemes and the type-3 PLL scheme through experimental tests.

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50μW RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm 2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

The enhanced phase-locked loop (EPLL) is one of the most famous PLLs in single-phase applications and a versatile tool for different signal processing applications, especially for the grid synchronization of power converters. Recently, it has been proved that the EPLL has a quite narrow stable zone (compared to its unstable zone) in the positive parameter space from a small-signal point of view. This zone will be even more narrow if maintaining a minimum stability margin is required. This article aims to modify the EPLL structure to improve its stability margin, and at the same time, make it unconditionally stable in the positive parameter space from a small-signal point of view.

In the electrical power and energy (EPE) area, the traditional concept in designing the synchronization system of power converters is using the phase-locked loop (PLL) concept. An alternative way is using the frequency-locked loop (FLL) concept, which is also known as the adaptive notch filter, adaptive noise cancelation technique, gradient descent estimator, adaptive observer, D-estimation method, and transformation angle detector, among others names. Along with the increased popularity and application of FLLs in EPE systems, the misconception about this design concept is growing. To be more exact, most EPE research communities introduce FLLs as synchronization systems of different properties compared to PLLs. This article aims to explain the main reasons behind this misconception and contribute to dispelling it.

© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works This article proposes a family of phase-locked loop schemes based on sliding modes. The use of sliding mode algorithms ensures fast response and global stability. In particular, two new algorithms are presented, both based on a complex framework for representing three-phase signals. This article compares the obtained algorithms with the traditional schemes, and a faster response is obtained when sliding modes are used. Additionally, as an application example, the algorithm is combined with a complex-coefficient filter that allows an easy identification of both positive and negative sequence harmonics. The proposed algorithms are illustrated by numerical simulations and experimentally validated using a digital signal processor.

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of -247dB, and normalized TR and area (FOMTA) of -262dB.

Phasor Measurement Units (PMUs) are measurement devices long used in transmission systems and today even more essential for a proper monitoring of distribution grids. The expected massive penetration of distributed energy resources (DERs) is slowly taking place, carrying along a new set of challenges that put to test traditional instruments and requiring more performance and flexibility to adapt to this evolving scenario. Cheap devices based on single board computer (SBC) are proving to be a valid alternative to traditional PMU architectures, able to combine together high-performance, great versatility and low-cost. However, such devices lack a proper modeling of their measurement errors that conversely would be extremely useful for improving their design and evaluate their performance in accordance with the relevant standards. The paper intends to fill this gap by discussing the error sources and their effects on the observed signals. An analysis of error statistics is presented, in order to give a more complete metrological characterization., 10 pages, 6 figures, 4 tables

This paper proposes the solution for decreasing of the reciprocating compressor noise and vibrations, which happens at stoppage. These vibrations and resulting noise are caused by the gas pressure in the cylinder, which impacts the compressor's piston and can reverse the motor at stoppage. To avoid this situation the motor must be stopped, when the gas is not pressurized, i.e., at the desired mechanical position, however motor is not equipped with a mechanical position sensor as the control system utilizes an electrical speed and position estimator. As a rule, it is impossible to estimate the mechanical position using an electrical position, however it has been noticed that at low speeds a detrimental feature of reciprocating compressors - varying load torque can help identify the mechanical position. Load torque impacts the quadrature current, making it oscillate at the mechanical frequency of the motor, so this mechanical frequency and position can be estimated using a Phased Locked Loop (PLL) algorithm, applied to the quadrature current.

Frequency-domain dissipativity of the converter admittance provides an intuitive approach to analyze wideband resonances due to the interactions with the grid. Although the reasons for high- and low-frequency resonances are different, it is found that the proportional capacitor voltage feedforward (CVF) can affect and reshape the converter admittance in a wide frequency range. To enhance wideband dissipativity under a weak/capacitive grid, a proportional-integral (PI)-derivative CVF is proposed in this article. Specifically, high-frequency dissipativity can be guaranteed through the multisampling control (MSC) with proportional-derivative CVF. The low-frequency nondissipative region caused by the phase-locked loop (PLL) and proportional CVF can be compensated through multiorder integrations. In light of grid frequency disturbances, modified integrators are further proposed for the multiorder integrations. The proposed method also applies to the conventional double-sampling control (DSC) with regard to the low-frequency dissipativity enhancement. Finally, experiments validate the proposed control method.

The interaction of a grid-connected voltage-source converter with a weak grid is of significant interest. In this paper, the converter together with the grid impedance is modeled as a single-input single-output (SISO) system. Provided that certain assumptions hold, this allows us to apply the standard SISO Nyquist stability criterion for stability analysis and controller design. The derived model is verified against time-domain simulations and experiments. The method facilitates the design of the converter control system with adequate stability margins.

Wandering spurs are a little-studied phenomenon seen in MASH and SQ-digital delta-sigma modulators. They take the form of frequency-modulated spurs which periodically appear in-band. Since modulators are often employed as divide ratio controllers in fractional-N phase lock loops, these spurs can feed into the output phase noise spectrum. In this paper, we explain the mechanism which creates the wandering spurs and offer a prediction for the behavior of these spurs in the MASH 1-1 modulator. Simulation results are presented which confirm our theoretical predictions. Enterprise Ireland Irish Research Council Science Foundation Ireland

Power factor correction (PFC) converters are widely employed for ac/dc conversion to fulfill the applicable standards while ensuring high efficiency. Current-sensorless controllers in PFCs simplify the interaction between power and control circuits, improving noise immunity. This paper reviews the state-of-the-art in-line current control techniques, identifying relevant contributions that incorporate predictive algorithms and eliminate the current sensor. Furthermore, it evaluates two approaches for current-sensorless PFC. The first is applicable to converters with diode bridge and includes a high-resolution digital control loop to cancel the estimation errors. The second, valid for bridgeless PFCs, is a new current-sensorless control, which includes a fast compensation of the prediction errors with a third-harmonic-dependent function generated from a phase locked loop. This compensation modifies the duty cycle sequence obtained from the controller, ensuring the matching of the line current with the reference obtained from the line voltage. The two evaluated approaches are investigated via computer simulations and experimentally.

Phase noise is one of the fundamental performance parameters in modern radar, communication, spectroscopic, and metrological systems. In this paper a phase noise theory has been developed for FMCW radar systems. A new design equation has been derived to specify the maximum bound on the allowable source phase noise level in radar systems. The non-linear phase noise decorrelation function due to coherent mixing has been analysed for propagation delays less than the coherence time of the reference oscillator, and the spectral broadening of target responses has been discussed for delay times greater than the coherence time. The effects of the subsystems in the transceiver chain are presented and a new model of phase noise in ADCs is discussed. Phase noise modelling techniques are presented, followed by a comparison of a PLL frequency synthesiser with a low-noise frequency synthesiser to demonstrate the reduction of phase noise sidebands for improved detection and tracking performance. Practical measurements from two millimetre wave FMCW radar systems utilising the two frequency synthesisers have been presented to validate the developed theory.

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of -106 dBc/Hz [figure of merit (FoM) of -239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop.

This paper applies the adaptive gradient descent method to the second-order generalized integrator (SOGI) filter in order to find an online estimation algorithm for the grid frequency, which leads to the proposal of three possible estimators. One of them is identical to the frequency-locked loop algorithm reported in the literature, which proves that it should be understood as a gradient descent estimation algorithm and not as a “frequency locked loop.” The proposed gradient descent estimators are simple and suitable to be implemented into a digital processor with small computational burden. However, due to the SOGI characteristics, the estimators show to be especially sensitive to subharmonic and dc-offset voltage distortion. These problems are removed adopting a cascaded double SOGI approach, which strongly increases the rejection capability to harmonics and enhances the response to voltage sags. Simulation and experimental results are provided to validate the proposed contribution.

This paper presents a compact low-jitter phase-locked loop (PLL) for high-frequency clock generation to be integrated in the front-end electronic readout of high energy physics experiments. The PLL is based on a LC voltage-controlled oscillator with a tuning range between 4.8 and 6 GHz. The PLL features a jitter below 4-ps rms with a power consumption of 18 mW. It has been designed in a CMOS 65-nm technology and occupies a silicon area of just 0.124 mm2. Irradiation tests showed that the design is still fully functional after a total dose of 2.5 MGy, with a moderate jitter increase.

International audience; Carrier synchronization is a fundamental stage in the receiver side of any communication or positioning system. Traditional carrier phase tracking techniques are based on well-known phase-locked loop (PLL) closed-loop architectures, which are still the methods of choice in modern receivers. Those techniques are well understood, easy to tune, and perform well under benign propagation conditions, but their applicability is seriously compromised in harsh propagation environments, where the signal may be affected by high dynamics, shadowing, strong fadings, multipath effects, or ionospheric scintillation. From an optimal filtering standpoint, the Kalman filter (KF) is clearly a powerful alternative, but the synchronization community seems still reluctant to exploit all the potential it has to offer. The purpose of this article is twofold: i) to review the basics and state of the art on both PLL and KF-based tracking techniques and ii) to present and justify the reasoning behind the systematic use of KF-based tracking approaches instead of the well-established PLL-based architectures from both theoretical and practical points of view. To support the discussion, two specific scenarios of interest to the aerospace community are numerically evaluated: robust carrier tracking of global navigation satellite systems' signals and synchronization in a deep space communications system.

A 4.48-GHz type-II charge pump fractional- ${N}$ PLL implemented in a 0.18- $\mu \text{m}$ BiCMOS process is presented. The divider controller’s output is processed using a novel block, the probability mass redistributor, which statistically reconfigures the modulation noise such that fractional spurs are minimized. Measurements demonstrate in-band fractional spurs of −80 dBc. The solution, which is a drop-in modification of a conventional MASH structure, incurs a modulator area increase of 22%, and can be used in conjunction with other linearization strategies.

Integer boundary spurs appear in the passband of the loop response of fractional- ${N}$ phase lock loops and are, therefore, a potentially significant component of the phase noise. In spite of measures guaranteeing spur-free modulator outputs, the interaction of the modulation noise from a divider controller with inevitable loop nonlinearities produces such spurs. This paper presents analytical predictions of the locations and amplitudes of the spurs and accompanying noise floor levels produced by interaction between a divider controller output and a PLL loop with a static nonlinearity. A key finding is that the spur locations and amplitudes can be estimated by using only the knowledge of the structure and pdf of the accumulated modulator noise and the nonlinearity. These predictions also offer new insights into why the spurs appear.

This article revisits the design of the current controller for grid-connected voltage-source converters (VSCs), considering the dynamic impacts of the phase-locked loop (PLL), weak grids, and of voltage feedforward (VFF) control. First, a single-input single-output transfer-function-based model is proposed to characterize the interactions of control loops. It is analytically found that the proportional gain of the current controller essentially aggravates the instability effect of PLL in weak grids, while the cutoff frequency of the low-pass filter used with the VFF loop has a nonmonotonic relationship with the PLL-induced instability. Then, based on these findings, a guideline for redesigning the current controller of PLL-synchronized VSCs is developed, which enables a codesign of the current controller and VFF controller. Finally, simulation and experimental results confirm the validity of theoretical analyses.

This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of -100 dBc/Hz at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz. European Research Council

Grid synchronization instability issues and low frequency oscillations between synchronous generators exist in electrical power system. This kind of stability issue happens between paralleled power converters is also reported. Analysis based on small-signal model of inverters with phase-locked loops (PLL) has been proposed. Different from that approach, which needs detailed inverter and controller parameters, this paper proposes an impedance-based analysis method to analyze the grid-synchronization stability issue in paralleled three-phase converter systems. The proposed method shows that the multivariable generalized inverse Nyquist stability criterion (GINC) can be used to predict the system stability based on the grid and inverter impedances in the synchronous d-q frame. Furthermore, the instability is found to be caused by qq channel impedance interaction. Experimental results verify the analysis and the proposed method.

This paper presents a novel closed-loop digital control scheme to maintain proper interleaving operation of a multi-channel boundary-conduction-mode (BCM) boost converter used in power-factor-correction (PFC) applications. The proposed control scheme is suitable for implementation on a low-cost microcontroller. This is made possible by executing the control scheme at a constant sampling rate that is much slower than the maximum switching frequency of the converter. The performance of the control scheme is further improved by using an adaptive gain that scales with the on-time of the converter, which provides optimal phase-shift control and stability under all operating conditions. The digital closed-loop control scheme is validated experimentally on a 3-channel 1 kW prototype ac-dc converter. The converter has an output voltage of 400 V and a universal input voltage range of 85 V to 265 V. The prototype converter uses a low-cost microcontroller while demonstrating correct interleaving operation.

Grid interfacing power converters are indispensable for renewable energy conversion schemes. Fast and precise detection of grid signal parameters is essential for effective operation and control of these converters. For such applications, synchronous reference frame phase-locked loop (SRF PLL) involving two orthogonal signals is widely deployed. For singlephase system, this requires another signal orthogonal to the input. In this paper, single-phase SRF PLL with fixed sampling period sliding discrete Fourier transform (SDFT) filter as orthogonal signal generator is proposed. Additionally, this filter is capable of rejecting dc offset and harmonics present in the grid voltage. With this arrangement, loop filter of PLL need not be equipped with filtering capability. Therefore, PLL could be designed with larger bandwidth which will result in better transient performance. However, SDFT output will be erroneous with asynchronous sampling, under grid frequency drift.With suitable study, relation between those errors and deviation of frequency from nominal value is established. Using this relation, error compensation at any grid frequency can be achieved. To validate the proposed method, various grid abnormalities are emulated with the aid of programmable power source and dSPACE realtime controller board. The effectiveness of the proposed scheme is demonstrated through experimental investigations., by Chandrasekaran Subramanian and Ragavan Kanagaraj

Phase-locked loops are important building blocks for several different applications. Modern design and implementation of these circuits is largely advantaged by a mixed analog/digital simulation approach since phase locked loops are stiff systems and a full analog representation is in general too large to simulate in reasonable time. Even though current algorithms, based on a mixed analog/digital representation, lead to models characterized by outstanding properties, they do not allow efficient simulations of important periodic and small signal features such as modulation/demodulation or noise effects. In this paper a novel, reliable and efficient method is proposed that overcomes those limitations and makes possible to evaluate both modulation/demodulation and noise effects in the widely adopted class of type-II phase-locked loop circuits based on a digital three-state phase-frequency detector.

In an increasingly noisy society, methods of reducing noise are becoming more important. This paper proposes an analog electroacoustic circuit for active control of narrow-band low-frequency acoustic noise using adaptive filtering techniques. The circuit aims at producing antinoise, which is acoustically added to the disturbing noise to produce an error signal that is fed back to the circuit. The proposed circuit is a modified Kerwin-Huelsman-Newcomb biquad filter that tunes itself to the incoming noise frequency using the zero tuning techniques. The circuit was implemented on a printed circuit board and it was successful in reducing noise by 15-20 dB in open space. Active noise control specifically for narrow-band noise cancellation using adaptive analog filters seems to be a better solution than its digital signal processing counterpart in speed, cost, and robustness. ? 2004 IEEE.

A low-power transceiver for ISM applications in the 868-MHz band has been integrated in a 0.8-/spl mu/m BiCMOS technology. The receiver part is based on the super-regenerative principle. The system includes two time-shared control loops, one for the selectivity and sensitivity control and one for the frequency control (PLL). The receiver with its PLL draws 3.6 mW for a sensitivity of -105 dBm and the emitter current consumption is 6 mA for a 0-dBm output power. A 2.4-V operation voltage allow the use of a two-batteries solution.

The proper operation of grid-connected power electronics converters needs using a synchronization technique to estimate the phase of the grid voltage. The performance of this synchronization technique is related to the quality of the consumed or delivered electric power. The synchronous-reference-frame phase-locked loop (SRF-PLL) has been widely used due to its ease of operation and robust behavior. However, the estimated phase can have a considerable amount of unwanted ripple if the grid voltage disturbances are not properly rejected. The aim of this paper is to propose an adaptive SRF-PLL which strongly rejects these disturbances even if the fundamental frequency of the grid voltage varies. This is accomplished by using several adaptive infinite-impulse-response notch filters, implemented by means of an inherently stable Schur-lattice structure. This structure is perfectly suited to be programmed in fixed-point DSPs (i.e., it has high mapping precision, low roundoff accumulation, and suppression of quantization limit cycle oscillations). The proposed adaptive SRF-PLL has been tested by means of the TI TMS320F2812 DSP. The obtained experimental results show that the proposed synchronization method highly rejects the undesired harmonics even if the fundamental harmonic frequency of a highly polluted grid voltage abruptly varies. © 2011 IEEE., This work was supported by the Spanish Ministry of Science and Innovation under Grants ENE2009-13998-C02-02 and ENE2006-15521-C03-02.

How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.