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A type of multilayer microstrip diplexer with highlyselectivewidebandfiltering channels is reported. Its closely-spaced fourth-order passbands are attributed to two circuit parts: (i) two third-order quasi-elliptic-type microstrip-to-microstrip wideband vertical transitions and (ii) a shunt two-stub dual-band bandpass filter (BPF) junction printed on the top layer. The two microstrip vertical transitions are developed by means of open-/short-circuitended microstrip lines and slotline stepped-impedance resonators (SIRs), respectively, and they correspond to the constituent lower and upper channels. The shunt dual-band BPF junction produces one additional transmission pole and one more pair of close-topassband transmission zeros (TZs) for each channel to further increase their filtering selectivity. The RF theoretical foundations and design procedure of the engineered broadband diplexer are detailed. For practical-validation purposes, a proof-of-concept prototype of two-layer fourth-order microstrip wideband diplexer is simulated, manufactured, and tested. Its measured lower and upper channels has two closely-spaced sharp-rejection passbands with center frequencies of 1.496 GHz and 2.759 GHz and 3-dB fractional bandwidths of 62.83% and 24.83%, respectively, while featuring power-isolation levels above 27.39 dB from 0.5 to 4 GHz., European Commission, Agencia Estatal de Investigación

Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been introduced to challenge the security foundations of locking schemes. These attacks are able to recover a significant percentage of the key without having access to an activated circuit. This paper address this issue through two focal points. First, we present a theoretical model to test locking schemes for key-related structural leakage that can be exploited by machine learning. Second, based on the theoretical model, we introduce D-MUX: a deceptive multiplexer-based logic-locking scheme that is resilient against structure-exploiting machine learning attacks. Through the design of D-MUX, we uncover a major fallacy in existing multiplexer-based locking schemes in the form of a structural-analysis attack. Finally, an extensive cost evaluation of D-MUX is presented. To the best of our knowledge, D-MUX is the first machine-learning-resilient locking scheme capable of protecting against all known learning-based attacks. Hereby, the presented work offers a starting point for the design and evaluation of future-generation logic locking in the era of machine learning., Comment: Accepted at IEEE TCAD 2021

Silicon-based optical media present several desirable properties for a wide range of applications. Herein, we propose a novel hybrid integration scheme that combines a silicon photonics platform and a 5.5%--silica planar-lightwave circuit (PLC) platform. By exploiting the performance advantages of each platform, we fabricated a polarization-insensitive low-crosstalk 8 8 silicon photonics switch butt-jointed with a compact 5.5%--silica PLC-based 100-GHz 8-channel arrayed waveguide grating (AWG). The device was driven by a smartphone-sized (9 cm 13.5 cm) control board. The fabricated device exhibits a fiber-to-fiber insertion loss of 12.6 dB, an average polarization-dependent loss of less than 0.57 dB, and less than -40 dB leakage to non-target output ports. We also demonstrate two uses of the proposed device. The first is the DEMUX and Switch operation, in which the spectrally divided light by the AWG is routed to an arbitrary output port by a subsequent switch. The second is the Switch and MUX operation, in which arbitrary wavelengths from arbitrary input ports are merged by the AWG. No spectral degradation was observed in either operation. These results demonstrate the potential of the 5.5%--PLC/silicon photonics hybrid platform for compact, low-power, and fast-switching applications.

This paper presents a selective laser melting (SLM) 3-D printed Ku-band diplexer using dual-mode resonators with high thermal stability. The diplexer is designed using dual-mode dimpled ellipsoid resonators which enables the diplexer mechanically self-supported in fabrication. Hence, the design has higher compatibility with the SLM printing process and the design can be extended to multiplexers with more channels. The excellent thermal stability is benefited from both the 4J36 invar alloy material with a lower coefficient of thermal expansion (C.T.E) as well as the tailored SLM printing process. Electrical and thermal performances of the diplexer are measured, showing that the fabricated diplexer is with average insertion losses of 0.69dB/0.42dB, return losses of >14dB, and centre frequency shifts of 5.62MHz/3.75MHz (

New transmission techniques for short-reach optical transmission applications especially datacenter interconnections are highly expected to break current bandwidth bottleneck, among which mode division multiplexing (MDM) based on few-mode fiber (FMF) is promising by exploring different linearly-polarized (LP) modes or mode groups as spatial transmission channels. However, it has been a great challenge to deal with degenerate modes in FMFs. In this paper, a FMF design utilizing multiple ring perturbations in fiber core to suppress modal crosstalk during fiber transmission is firstly proposed and a 6-LP-mode double-ring-core (DRC) FMF is fabricated with a high minimum refractive index difference (min|neff|) of 1.4910-3 among all the modes. Secondly, a novel degenerate-mode-selective coupler (DMSC) converting each degenerate LPmn mode into the LP11 mode in a two-mode fiber is proposed. Then intensity-modulation/direct-detection (IM/DD) MDM transmission scheme without any digital signal processing (DSP) can be realized utilizing mode multiplexer/demultiplexer (MUX/DEMUX) consisting of cascaded mode-selective couplers (MSC) and DMSCs, in which each degenerate or non-degenerate LP mode is considered as an independent transmission channel. Then based on the proposed DRC-FMF and mode MUX/DEMUX, we demonstrate a 4-LP-mode prototype system using commercial single-mode 10 Gbps SFP + modules and 4K video transceivers without any hardware or software modifications. Finally, the intra-LP-mode dispersion (ILMD) effect in a weakly-coupled FMF is analyzed and a modified fixed-analyzer method is proposed for its measurement. Experimental results show that it may be one of the major impairments for IM/DD MDM transmission.

This article presents a new compact multiplexer structure and its design approach, based on a novel resonant manifold. Different from typical transmission-line-based manifold multiplexers, the proposed manifold junction is formed of coupled resonators, so that the manifold also contributes to the filtering poles and selectivity in the passbands. The all-resonator configuration achieves a more compact footprint than the conventional manifold. This multiport filtering network can be represented by a single coupling matrix which can be obtained by using a robust optimization-based method. Tailored channel frequency allocation schemes are presented for the proposed multiplexers with a different number of channels. To validate the proposed concept, a triplexer and a five-channel multiplexer, both at X-band, are designed and tested using rectangular waveguide technology. Good agreements have been achieved between the measurement and simulations. Comparisons have been made with conventional multiplexers.

To cancel the multipath self-interference at the receiver of a wideband in-band full-duplex (IBFD) multiple-input multiple-output (MIMO) radio-over-fiber (RoF) transmission system, a photonic-assisted approach is proposed and experimentally demonstrated. A multipath optical tunable delay line (MOTDL) module with a large adjusting arrangement and high tuning precision is designed to manipulate the local reference signals, which are modulated onto several optical wavelengths and then poured into the MOTDL via a dense wavelength division multiplexer (DWDM). By tuning the time delay and attenuation of each path in the MOTDL, all the self-interference signals can be cancelled from other local transmit antennas of the MIMO RoF transmission system, and the desired radio frequency (RF) signal can be recovered. A proof-of-concept experiment is carried out to verify the feasibility. Results show that at the receiver of a 3 3 MIMO RoF transmission system, the multipath self-interference cancellation depths of 30.18 dB, 24.9 dB, 22.7 dB, and 20.88 dB at 16.6 GHz are achieved for the bandwidths of 100 MHz, 500 MHz, 1 GHz, and 2 GHz, respectively.

Mode-locked lasers with low noise performance, such as low timing jitter and relative intensity noise are essential for high-precision applications. In this letter, we demonstrated a 122-MHz all-polarization-maintaining mode-locked Er-doped fiber laser based on a nonlinear amplifying loop mirror. A hybrid component integrating a wavelength division multiplexer and a phase shifter is applied to increase the repetition rate. The relative intensity noise is 0.004% and 0.76% rms (integrated from 1 MHz to 100 Hz) from two output ports. The timing jitter characteristic is measured by the delayed optical heterodyne method. The timing jitter is ~1.9 fs rms (integrated from 1 MHz to 10 Hz) of both two output ports. The origin of the timing jitter of this laser is analyzed numerically based on the well-established theoretical model using the laser’s repetition rate, cavity dispersion, etc.

This article presents a 220-GHz four-channel, noncontiguous, and manifold-coupled waveguide multiplexer for future terahertz (THz) multichannel communication application. The multiplexer is composed of four Chebyshev bandpass filters based on metal waveguide technology. Through a unique design in which the tuning dimensional variables are reduced to 14 and a co-design of low-order electromagnetic (EM) distributed models and full-wave EM models, the design optimization is achieved with a good computational efficiency and design accuracy. The proposed multiplexer is fabricated by high-precision computer numerical control (CNC) milling technology, in which the fabrication errors are evaluated to be within ±3 μm. The measured results exhibit 1.7 dB of in-band insertion loss and better than 15 dB of average common-port return loss for each of the channel filter. The measured results are all in good agreement with the simulated ones, thereby validating the complete design procedure.

In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.

We design and experimentally demonstrate an ultra-compact dual-mode mode-division multiplexing (MDM) photonic integrated circuit (PIC), which supports on-chip optical signal mode-order-based routing and mode-independent broadcasting. The MDM circuit is composed of inverse-designed three multiplexers, one 3-dB power splitter, three bends and one crossing based on photonic-crystal-like subwavelength structure. The measured excess loss and crosstalk of the fabricated MDM circuit are lower than 5.9 dB and −13 dB over a 60 nm observable wavelength span, respectively. The experiment results of single-channel 25 Gbit/s optical signal transmission show that only 1.2-dB power penalty is introduced through the MDM circuit at a bit-error-rate of 10−9.

Mode division multiplexing (MDM) has attracted great attention in recent years to increase the network capacity. To apply MDM in data center applications, a low-cost and low power consumption system is desired. In this letter, we utilize 850-nm single-mode VCSEL as the laser source and report mode division multiplexed transmission over a standard single-mode fiber, which is two-mode at 850 nm. Due to the small spot size and low numerical aperture, single-mode VCSEL can be coupled into single-mode fibers with low loss. The mode multiplexer and de-multiplexer devices are designed and fabricated based on fiber mode selective couplers using Hi780 fiber as the 850-nm single-mode launch and receiving fiber and standard single-mode fiber as the few-mode transmission fiber. The MDM system supports two channels, corresponding to the LP01 and LP11 mode in the few-mode transmission fiber. Detailed characterizations of the multiplexer and de-multiplexer are conducted including the insertion loss and crosstalk measurements. System transmission at 25 Gb/s shows error free performance over 1-km standard single- mode fiber for both channels. The utilization of VCSEL and standard single-mode fiber can potentially provide a low-cost solution for MDM systems in data center applications.

A 3D architecture made up of a CMOS layer combined with a 3D stack of bipolar memristor crossbar arrays provides an innovative approach to hardware support for utilizing the strength of CMOS combined with the strength of memristors. Memristors have been evaluated for implementing a broad spectrum of applications such as memory, computations, hardware-based security primitives, cryptography, etc., and numerous studies have shown that memristors are desirable candidates for such applications. This paper proposes a novel 3D memristive crossbar architecture (i.e., a stack of memristive crossbar arrays built on top of CMOS substrate) with a specific focus on the way of connecting the crossbar arrays to the CMOS layer. The proposed architecture is configurable and allows restructuring crossbar arrays and creating 1D arrays with adjustable sizes. The proposed architecture enables parallel and pipeline computations where data can move or be processed in planes perpendicular to the stacked crossbar arrays. In addition, the proposed architecture is scalable meaning that stacks of crossbar arrays can be connected without additional overhead. This paper shows examples of implementing a full adder, a 4-bit look-ahead carry generator, and an 8-bit multiplexer. Simulations and area, delay, and power analysis demonstrate the behavior of the proposed 3D circuit.

This article presents a hardware- and power-efficient RRAM-based neural network capable of online learning. The network is modularized in consideration of scalability and consists of 11 modules. Each module comprises two 25 × 25 RRAM crossbar arrays, four analog multiplexers, and one neuron chip. A stochastic neuron that performs both quantization and activation of the column current flowing through the RRAM array is used to perform online learning without using the high-resolution analog-to-digital converters and digital-to-analog converters. The impact of the initialization of the RRAM device on the network performance is analyzed and a fast yet effective method of initialization is also presented. The network consists of three fully connected layers with 100 input and 10 output neurons. The two hidden layers are made up of 50 and 25 neurons, respectively, and a total of 13 × 103 synapses are implemented by combining 21 RRAM arrays. The neuron chip, which includes 32 neurons, is fabricated through a 0.18-μm standard CMOS process. The network achieves a classification accuracy of 93.4% for the reduced Modified National Institute of Standards and Technology database (MNIST) dataset and the energy efficiency of 38.1 teraoperations per second per Watt (TOPS/W), the highest efficiency among recently reported state-of-the-art RRAM-based neural networks.

This article presents a 120-GS/s 2:1 8-bit analog multiplexer (AMUX) in SiGe-Bipolar CMOS (BiCMOS) technology that exhibits the highest effective resolution reported for an AMUX in any kind of semiconductor technology. This article presents the design considerations that have led to this high resolution. In particular, it contains a discussion on the choice of an AMUX circuit concept to support high linearity. A frequency-domain explanatory model for the signal contribution to the effective number of bits (ENoB) in the presence of mismatch errors is presented and applied to the analysis of timing and signal gain mismatch in the AMUX setup. Typical ENoB versus frequency characteristics were identified and utilized to speed up ENoB simulations and to develop calibration procedures for the different mismatch types in the AMUX setup. The results of the analysis and the performance of the AMUX in the calibrated setup were proven by measurement results.

Polar codes are one of the recently developed error correcting codes, and they are popular due to their capacity achieving nature. The architecture of the successive cancellation (SC) decoder algorithm is composed of a recursive processing element (PE). The PE comprises various blocks that include signed adder, subtractor, comparator, multiplexers, and few logic gates. Therefore, the latency of the PE is a primary concern. Hence, a high-speed architecture for implementing the SC decoding algorithm for polar codes is proposed. In the proposed work, a novel restructuring of the 2bit-SC (2b-SC) precomputation decoder architecture is carried out to reduce the latency by 20% while reducing the hardware complexity. Compared to the 2b-SC precomputation decoder, the proposed architecture also has 19% increased throughput for (1024, 512) polar codes with 45% reduction in the gate count.

Polarization and mode division multiplexing are powerful tools for large-capacity parallel optical communications. Dual-polarization and mode-division multiplexed silicon photonic integrated circuit with ultra-small footprint is proposed and experimentally demonstrated. The circuits consist of a mode multiplexer, 3-dB power splitter and two demultiplexers which can simultaneously handle TE0, TE1, TM0 and TM1 mode. Compared with conventional device structure, the device footprint is scaled down via pixelated waveguide meta-structure. The mode multiplexer and the splitter have a footprint of only 6.8 μm × 6 μm and 6 μm × 5.25 μm, respectively. The fabrication tolerance on the nanohole size variations are studied, and the fabricated devices are systematically characterized. The measured insertion losses of the multiplexer and 3-dB power splitter are below 1.4 dB and 4.5 dB for all four modes within the wavelength range from 1530 nm-1570 nm. In the meantime, the measured maximum inter-mode cross talk is below -15 dB over a 30 nm bandwidth. The experimental results also indicate the power imbalance of the splitter is within 0.4 dB from 1530 nm-1570 nm. Since the demonstrated polarization and mode handling devices via pixelated meta-structures occupy significantly smaller chip area than conventional wisdoms, this work shows the potential for large scale and dense integration of polarization and mode division multiplexing system on photonic chip.

As part of the ATLAS experiment’s Phase-II Upgrade, improved trigger hardware and algorithms will be implemented onto a single-level architecture. The global trigger (GT) subsystem is a new firmware (FW)-focused project designed to meet stringent requirements from the high-luminosity runs of the large hadron collider (LHC). The global multiplexer (MUX) is the input aggregating stage of the GT; it performs three main tasks: 1) aggregating data from several sources, connected with more than 2300 input fibers, under different protocols; 2) time-multiplexing the incoming data, to sort the packets per bunch-crossing (BC) events, by compensating the relative skews across the various serial input channels; and 3) transmitting, in a round-robin fashion, the sorted BC data to the global event processor (GEP) array, which is the following stage of the GT subsystem and is composed of 48 nodes, each one processing a single BC event. Two MUX FW prototypes for the Global Feature EXtractor (gFEX, part of the liquid argon calorimeter trigger) inputs have been designed, implemented, and validated on a gFEX production board, for up to 72 input and output channels. A four-channel version has been completed with I/O interfaces and validated in a full-chain design, accepting 8b/10b encoded inputs at 11.2 Gb/s and transmitting at 25.78125 Gb/s under Xilinx Aurora 64b/66b protocol. The total latency has been benchmarked in all of its contributing subcomponents and proven to meet the requirements from the Technical Design Report for the Phase-II Upgrade of the trigger and data acquisition system.

A CMOS image sensor (CIS) that performs compressive sensing (CS) image encoding without compromising the operating speed and hardware complexity is presented in this article. The conversion rate and the frame rate of the sensor are increased by using a high-order sigma-delta (ΣΔ) analog-to-digital converter (ADC) to obtain linear measurements of selected pixel values for CS encoding. Image distortion caused by the nonconstant weight function of high-order ΣΔ ADCs is eliminated by using the proposed sampling technique. The sampling technique makes the effective weights of the inputs to the ADC equal by applying a solution for the set partition problem. In addition, unlike the existing block-based CS encoding scheme that requires complicated analog multiplexers, the proposed column-based CS encoding scheme can be implemented in a hardware-efficient column-parallel fashion, as in conventional CISs. The CIS is fabricated in a 0.11-μm 1P4M CIS process, and the sampling technique and encoding scheme are successfully demonstrated. It achieves a readout noise of 2.63 e-rms and a dynamic range of 67.96 dB with a power consumption of 56.38 mW. The resulting figure of merit is 0.375 e-·nJ, which is the lowest among those of recently reported state-of-the-art CS-CISs.

A broadband silicon four-mode (de)multiplexer [(De)MUX] is proposed and experimentally demonstrated based on subwavelength gratings (SWGs)-assisted triple-waveguide couplers (TWCs), which can (de)multiplex TE0, TE1, TE2, and TE3 modes. The mode interaction is enhanced, benefitting from both the triple-waveguide coupling and subwavelength structures. The proposed four-mode (De)MUX is composed of three SWG-assisted TWCs connected by three linear tapers. The experimental results show that the 3-dB bandwidths are 100 nm, 76 nm, 90 nm, and 95 nm for the TE0, TE1, TE2, and TE3 modes, respectively. The corresponding insertion losses are 0.2, 1.8, 1.3, and 1.7 dB, and the mode crosstalks are -23.3, -17.7, -15.5, and -17.0 dB at the 1550 nm wavelength. The proposed device can work as a mode-(De)MUX compatible with wavelength division multiplexing (WDM) to increase the transmission capacity of on-chip optical interconnects.

We demonstrate a compact ($367 \times 67 \, \mu {\text{m}}^2$) four-channel wavelength division multiplexer using an arrayed waveguide grating based on multimode interference couplers, and built on a monolithic silicon photonics platform. The design is particularly attractive due to the thin device layer. A semi-numerical approach was used for device design and simulation. Optical measurements were found to be consistent with simulation results. The device channel spacing, 3-dB bandwidth and crosstalk were measured to be 97 GHz, 87 GHz and 9.6 dB, respectively, for the designed wavelength of operation near 1310 nm.

We proposed a new kind of add-drop multiplexer based on $\pi $ phase-shifted antisymmetric Bragg grating ( $\pi $ -ASBG). Light resonance is formed in the $\pi $ -ASBG with mode conversion between backward fundamental transverse electric (TE0) mode and the forward first order transverse electric (T1) mode. With the aid of the TE1 mode generated in the $\pi $ -ASBG, add-drop multiplexer can be designed. As examples, two multiplexer structures based on single- and dual-bus resonator, on silicon-on-insulator (SOI) platform have been studied in detail. Besides, no light is reflected to the input port, if the structure is carefully designed with critical coupling condition satisfied. For the fabricated add-drop multiplexer based on single-bus resonator, the extinction ratio is 23.90 dB and full width at half maximum (FWHM) is 0.33 nm at the through port. For the fabricated add-drop multiplexer based on dual-bus resonator, the extinction ratio is 17.22 dB and FWHM is 0.29 nm at through port. The results show that proposed structures provide a new method to realize add-drop multiplexer and other integrated optical filters for optical communications and sensors.

This article presents a novel quad-ridge cavity resonator to realize a trimode response based on the TE101, TE011, and TE111 modes. The basic structure of the quad-ridge resonator (QRR) contains four ridges located at the center around the cavities. With an appropriate combination of the main parameters (length and width of the resonator and heights of the ridges), the first three TE resonant modes can be flexibly controlled, and each mode can carry the signal of a channel. Compared with a traditional rectangular cavity, the QRR provides more design freedoms for controlling the first three TE resonant modes and features a wider spurious-free window. The electric field distributions of the QRR are thoroughly analyzed to guide the realization of a filtering response. Intracavity coupling is achieved by an all-iris structure, including horizontal and vertical coupling slots with offsets to the cavity center, capable of easy fabrication and assembly. A nine-pole triple-band filter and a 12-pole triplexer are designed and manufactured to validate the concept. A comparison with other reported multiplexers indicates that the proposed triplexer exhibits the advantages of size reduction and high isolation.

In this article, a modularized charge equalizer is proposed. In the proposed topology, N series cells are divided into K modules and each module consists of J series cells and its multiplexer switches. A multioutput transformer is used as temporary energy storage. Each of the transformer outputs is connected to one of the K modules and targets the cells in its module. In this way, at the same time K cells are targeted simultaneously and the speed of balancing has increased. In the proposed circuit, energy can be transferred by string to cell, cell to string, and cell to cell methods. In addition, it can be transferred between modules and equalize them. Therefore, the proposed topology is very flexible and can circumvent the limitations of each method and use the appropriate method in the right place. Also, a step-by-step method for command the multiplex switches is proposed. To illustrate the correctness of the circuit operation, a prototype is implemented to balance the charge of four lithium-ion battery cells. The experimental results confirm the correctness of the proposed circuit operation.

This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) voltage-mode transmitter (TX) with a four-tap feed-forward equalizer (FFE). A two-step coarse-/fine-tuning technique is adopted in the voltage-mode FFE to reduce the number of front-end slices while maintaining sufficient resolution. In addition, the device sizes in the preceding multiplexer (MUX) and predriver can be enlarged, relaxing the self-loading effect from the layout and improving the bandwidth. An analog impedance control loop is applied to achieve output impedance matching and maintain the corresponding weighting between coarse- and fine-FFE stages. The quarter-rate 4:1 MUX incorporates an automatic phase alignment technique to eliminate the timing constraint. As a result, all of the retiming latches can be removed, saving significant power. Designed and fabricated in 40-nm CMOS, the PAM-4 TX demonstrates a high-quality eye diagram at 112 Gb/s with 3.89-pJ/b energy efficiency under a chip-on-board assembly with 5.5-dB Nyquist loss.

Silicon photonics can be used to increase the versatility of wavelength division multiplexing (WDM). Ultra-dense wavelength division multiplexing (uDWDM) shrinks channel spacing between WDM channels to decrease guard bands and increase spectral efficiency. Microring modulators (MRMs) provide a simple solution for uDWDM transmitters - they require no multiplexer/demultiplexer. When used with comb lasers, MRMs provide extremely compact and low power solutions. The spectral efficiency is limited by interchannel interference (ICI) from incomplete isolation of channels. We report an MRM-uDWDM transmitter achieving channel spacing comparable to the symbol rate in each WDM channel, reaching a spectrum occupation of 80%. By choosing the correct operating point, we demonstrate experimentally our fabricated MRM chip design causes no discernable ICI power penalty. To the best of our knowledge, this is the first demonstration of MRM-uDWDM to support such dense channel spacing.

This paper demonstrates a hardware encryption algorithm that can be integrated directly with sensors on the same chip. In contrast to using power-hungry microprocessors and software implementations, the encryption algorithm was based on a Lorenz chaotic system and was implemented as time scaling chaotic shift keying (TS-CSK). The coupled differential equations of TS-CSK were implemented using low power integrators, multiplexers, switches, and passive components. Both a single-ended and differential system was developed. The single-ended based system showed no oscillation, while the differential based system demonstrated oscillation. Experimental measurements of the differential system with an integrated temperature sensor demonstrated the ability to encrypt and decrypt the transmitted signal. The differential encryption/decryption system was implemented in 180 nm technology and operated with a 1.8 V power supply and 1.5 mW of power.

We demonstrate a dual-band two-mode (de)-multiplexer based on tapered asymmetric directional coupler (ADC). The working principle of the device relies on the conversion of the fundamental transverse electric (TE0) mode to the first order (TE1) mode. A phase-matching condition is applied across the O- and C-bands to broaden the operation wavelength of the device. Measurement performed on a mode division multiplexing (MDM) link formed by a back-to-back connected multiplexer and demultiplexer exhibited an insertion loss of less than 1.2 dB with cross talk better than 16 dB. The response is recorded over dual-bands, each with 100-nm bandwidth covering 1260-1360 nm and 1500–1600 nm (extends to the near L-band). The device is compact with an overall length of 75 μm.

Polymer waveguides are considered to be good candidates for optical interconnects application due to their advantages such as flexibility, good compatibility, and versatility for realizing 3D and micro structures. However, constrained by the limited degrees of freedom provided by template-based design approaches, there lacks a satisfying solution which achieves small footprint and low loss simultaneously. Inverse design has been proposed to improve the performance. However, most inverse design methods target at silicon-based optical devices optimization which has a relatively high refractive index difference. In this paper, we demonstrate an ultra-compact low loss polymer wavelength (de)multiplexer with spot-size conversion structure to interposing Si and optical fiber using gradient-based topology optimization and downhill simplex method. The 2-channel wavelength (de)multiplexer displays an excess propagation loss of 0.84 dB and 1.06 dB at 1310 nm and 1550 nm, respectively, with a total footprint of 245 × 35 $\mu$m$^2$. The 4-channel wavelength (de)multiplexer for coarse wavelength division multiplexing applications with 20 nm spacing (1270, 1290, 1310, and 1330 nm) with an excess waveguide propagation loss of 1.72 dB within 271 × 50 $\mu$m$^2$ has also been demonstrated and all the output ports of the polymer wavelength demultiplexing structure achieved a conversion efficiency over 90%.

Alternative data paths for the cascaded integrator-comb (CIC) decimator are presented that can be derived upon applying one or two modifications. In the first modification, the integrator-comb pair that surrounds the downsampling register is replaced by a simpler Integrate-and-Dump (ID) block that performs the same decimation task. The resulting data path is referred to as CIC-ID. In the second modification, the remaining comb filters are replaced by a timemultiplexed comb, and the resulting data path is referred to as CIC-ID-TMUX. Compared with a classic N -stage CIC, CIC-ID saves one arithmetic unit and one register, whereas CIC-ID-TMUX uses the same number of registers but trades ( N - 1) arithmetic units for a simpler two-to-one multiplexer. Both CIC-ID and CIC-ID-TMUX perform slightly fewer arithmetic operations per output sample because of the absence of the comb filter absorbed by the ID block. Pruning formulas for both architectures are presented along with implementation details.

Threshold logic (TL) circuits gain increasing attention due to their feasible realization with emerging technologies and strong bind to neural network applications. In this work, we devise techniques for automatic synthesis and verification of TL circuits based on constraint solving. For synthesis, we formulate a fundamental operation to collapse TL functions, and derive a necessary and sufficient condition of collapsibility for linear combination of two TL functions. An approach based on solving the subset sum problem is proposed for fast circuit transformation. For verification, we propose a procedure to convert a TL function to a multiplexer (MUX) tree and to pseudo-Boolean (PB) constraints for formal Boolean and PB reasoning, respectively. Experiments on synthesis show that the collapse operation further reduces gate counts of synthesized TL circuits by an average of 18%. Experiments on verification demonstrate good scalability of the MUX-based method for equivalence checking of synthesized TL circuits, and efficiency of PB constraint conversion in cases where the conjunctive normal form (CNF) formula conversion and MUX tree conversion suffer from memory explosion.

A broadband mode (de)multiplexer [(De)MUX] is proposed and experimentally demonstrated based on a triple-waveguide coupler (TWC) with the phase-matching of a multimode access-waveguide. The tolerance to the operating wavelength and fabrication error of the proposed mode (De)MUX can be relaxed with the aid of the wider access-waveguide and the middle waveguide. The optimized mode (De)MUX is with a coupling length of $48~\mu $ m and a broad bandwidth of >122 nm with the mode crosstalk of

The design of a novel 1 × M fold-back type wavelength selective switch (WSS), which has fewer waveguide crossings than a conventional integrated WSS, is reported. The WSS is composed of interleavers, 1 × M optical switches, and arrayed waveguide gratings (AWGs). Switches are combined with AWGs by fold-back waveguides, and each AWG works as both a demultiplexer and multiplexer thus avoiding center wavelength mismatch caused by fabrication errors. Waveguide crossings cause excess crosstalk and loss in lightwave circuits. By using a fold-back architecture the number of crossings can be reduced to less than half that of a conventional design. We discuss the operating principle, the design method, and the scalability of the fold-back type WSS. Furthermore, the switching operation of a 200-GHz spacing, 20-channel, 1 × 2 silicon WSS in a fold-back configuration on a 5 mm × 10 mm SOI chip is demonstrated. This has 15 waveguide crossings in a path, of which six are additional crossings with monitor waveguides. The average insertion loss and average extinction ratio are 29.6 dB and 10.9 dB, respectively.

Today, we are evident to the revolution of the automotive industry and its demand for high bandwidth sensor fusion. Multiple high bandwidth sensors are connected, generating tremendous amount of data to be transferred in real-time in harsh environment, i.e., multi-gigabit intra-vehicle networks. Plastic optical fiber (POF) is an attractive medium for these multi-gigabit intra-vehicle networks due to its inherent EM compatibility, galvanic isolation, low weight, high tolerance to mechanical vibrations, low bending loss, and easy handling. However, commercial off-the-shelf PMMA based POFs are bandwidth-length product limited. Here, we suggest increasing the spectral efficiency using spatial-division multiplexing (SDM). In this article, we have experimentally demonstrated a low cost and eye-safe 3 × 3 multiple-input multiple-output (MIMO) SDM system over a 15 meters multicore (MC) POF using commercial optical components, e.g., RC-LEDs and Si-PIN photodiodes. A 3 × 1 spot-based cores coupler spatial multiplexer was developed to couple the optical components with the MC-POF. This system achieved raw data rates of 1.5 Gb/s and 2.4 Gb/s using offline-processed MIMO equalization. The proposed system enables a flexible and scalable optical MIMO system that can meet the requirements of the automotive industry.

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates $0.43~\mu \text{J}$ and ${0.82~\mu \text {J}}$ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and $0.56~\mu \text{W}$ , respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates $1.25~\mu \text {J}$ per measurement, achieving a resolution of 18.7 mm at 0.55 m.

Logic locking is a new technique to prevent an integrated circuit from hardware Trojan, piracy, overbuilding, etc. Most of the well-known logic locking techniques are vulnerable to sensitization and cone based attacks. Though the existing techniques try to thwart these attacks, they are highly circuit topology dependent and require significant overhead. Therefore, this paper presents a new lightweight logic locking technique that effectively neutralizes the sensitization and cone based attacks. We further propose new multi key-input gates and a new replacement-based logic locking algorithm. The replacement of design gates with our multi key-input gates not only effectively prevents the key-sensitization and signal probability skew based removal attacks but also removes rare nets from design. On the other hand, our logic locking algorithm significantly increases the brute-force attempts against cone-based attack with minimum replacements by replacing the nodes which have the maximum number of fan-outs and paths to output nodes. We evaluate our technique using ISCAS benchmarks, and the results demonstrate that the proposed key-gates on average reduce 32 percent area-overhead over the XOR/MUX key-gates, whereas our algorithm on average doubles the effective key size while reducing 50 percent area overhead over the best-known technique.

A dual channel system based on a dual-parallel Mach–Zehnder modulator (DPMZM) is proposed for simultaneous measurement of angle of arrival (AOA) and Doppler frequency shift (DFS). The echo signals are received by two antennas and sent into two sub modulators (sub-MZMs) of the DPMZM respectively. The transmitted signal is fed into one of the sub-MZMs to act as a local oscillator signal. The upper and the lower sidebands of the output signal from the DPMZM are separated by a wavelength-division multiplexer (WDM) to form two channels. By measuring the power of the beating signal of the two channels, the AOA can be measured and the phase measurement error is less than 3.4° in the range of about 300° (The AOA is measured from ±10° to ±90°). Moreover, the system can measure DFS with the measurement error less than 0.07 Hz and determine the DFS direction by comparing the phase relationship between the two channels. The system structure is simple and compact, which is a simple and effective solution for modern radar and electronic warfare receiver.

In this brief, we show how to derive all the optimum multi-path delay commutator (MDC) fast Fourier transform (FFT) hardware architectures in terms of delays and multiplexers and calculate the number of such architectures. The proposed approach is based on analyzing the orders at the FFT stages that lead to optimum number of delays and multiplexers. The results show that there exist a large number of optimum MDC FFTs. This large design space can be explored in the future in order to design efficient MDC architectures that not only optimize the number of delays and multiplexers, but also other figures of merit such as the number of rotators or the input/output data order.

Wavelength Division Multiplexing (WDM) networks with reconfigurable optical add/drop multiplexers (ROADMs) realize automatic scheduling and restoration at the wavelength level and are therefore part of the solution to meet increasing bandwidth and routing flexibility requirements for transport networks. The wavelength selective switch (WSS) is the key component in all commercial ROADM systems. Liquid crystal on silicon (LCoS) technology dominates current WSS installations as LCoS-based WSS can support Flexgrid technology enabled networks, and high port counts with excellent performance. WSS designs are becoming increasingly specialized for a wide variety of applications. For single WSS used in broadcast and select (B&S) architecture, superior port isolation is key for the desired signal to be filtered from the whole spectrum. While for twin WSS deployed in route and select (R&S) nodes, many features are desired for various network applications. These include multiple common ports, premium ports with superior port isolation, and high port counts. Future WSS may be asked to address a number of different end user applications, and as such there is a demand for combinations of custom spectrum range, compact form factors, increased WSS port count, low cost, thermal and mechanical ruggedization. The first commercially available quad WSS is part of this increasing trend of utilization of WSS throughout network architectures.

The optical fiber deployed in the metropolitan infrastructure carrying high-speed WDM traffic data is used also for network surveillance, identifying and localizing the onset of vibrations and dynamic stress events, potentially dangerous for the integrity of the fiber telecom asset. A coherent approach is adopted in a counter-propagating interferometer to develop a sensing system exploiting the ring layout of the metro network. With respect to usual dual Mach-Zehnder interferometric sensors, where typically the reference arm is kept isolated, in our arrangement we use as reference arm a fiber inside the same deployed cable, minimizing the impact of the city strong environmental noise. Preliminary assessments of the proposed sensing solution have been experimented in a metro ring of 32-km standard single-mode fiber deployed in the city of Turin, Italy, devoted to telecom applications. The sensor is demonstrated to operate preserving the coexistence with the high-speed WDM telecom traffic. With respect to complex and expensive sensing solutions based on pulsed phase-OTDR techniques, in the present case continuous-wave counter-propagating optical signals are exploited and the spatial resolution in dynamic event localization depends only on the receiver sampling rate: in our implementation, by adopting off-the shelf low-cost commercial 20 MS/s sampling boards, 10-meter spatial resolution is experimentally achieved. The proposed sensing solution provides significant added value to the deployed metro fiber infrastructure and the same interferometric approach based on the counter-propagating layout can be easily exploited in metro networks even in case of presence of optical nodes equipped with reconfigurable optical add-drop multiplexers useful for WDM traffic routing.

Waveguide components have been widely explored for several decades, due to their inherent merits of low insertion losses, high quality ( Q ) factors, and a significant power-handling capacity. Historically, cavity-based narrowband filters and multiplexers have been explored and designed for base stations and satellite applications. Compared with using single-mode resonators (SMRs), the implementation of multiple-mode resonators (MMRs) in waveguide structures is a promising solution to dramatically reduce the circuit volume and improve the frequency selectivity. Taking advantage of MMR techniques, various innovative waveguide structures have been proposed for a wide range of application scenarios. This article presents an overview of advances in microwave multiple-mode waveguide components, including narrow-, wide-, and multiband filters; multiplexers; three-state diplexers; crossovers; and balanced/unbalanced elements. Representative examples and their results are comprehensively discussed and summarized.

We introduce recently developed space division multiplexing (SDM)-associated technologies into optical wireless communications (OWC) and propose to use incoherent and low-coherence spatial modes to realize optical broadcasting with reliable performance by mitigating coherent interference. We experimentally demonstrate reconfigurable optical beam steering using a programmable multi-plane light conversion (MPLC)-based mode multiplexer (MMUX) and realize point-to-multi-point optical wireless communications with low-loss up-link optical beam combining and reach extension using multimode fiber (MMF). Both incoherent and low-coherence spatial modes can be generated employing cost-efficient components such as a multimode vertical cavity surface emitting laser (MM-VCSEL) and broadband amplified spontaneous emission (ASE) noise source.

In this article, a beyond 1.6 Tb/s net rate pulse amplitude modulation (PAM) communication system is experimentally demonstrated for 20 m rack-rack optical interconnects with low cost intensity modulation direct detection (IM-DD) architecture, which is enabled by mode division multiplexing (MDM) and wavelength division multiplexing (WDM). The MDM with three linearly polarized modes is realized by a multiplane light conversion (MPLC) mode multiplexer with the maximum modal crosstalk less than – 20 dB. The experimental results show that 2.01 Tb/s (1.84 Tb/s net rate) PAM-6 signal carried on three modes and four wavelengths is successfully transmitted over 20 m standard OM2 multimode fiber (MMF) with the BERs of received signals from all channels below hard decision forward error correction (HD-FEC) threshold of 3.8 × 10–3. Look-up table (LUT) pre-distortion and Volterra nonlinear equalizer (VNLE) are employed for nonlinear impairment mitigation to improve the system performance. Compared to linear feedforward equalizer (FFE), 0.3 dB and 1 dB receiver sensitivity improvements are obtained by LUT and VNLE, respectively. To the best of our knowledge, our proposed scheme achieves the highest bit rate of 167.5 Gb/s per wavelength in MDM system with IM-DD structure. The experimental results show that our proposed PAM MDM communication scheme is a promising candidate for future 1.6 Tb/s short reach rack-rack optical interconnects.

Optical fiber transfer delay (OFTD) measurement with high accuracy and stability is an urgent demand for many applications such as fiber-optic sensors and fiber-based distributed systems. In this article, we propose a novel method using fiber-optic microwave interferometry to meet the above practice demand. Two incoherent optical carriers with different wavelengths are coupled into an intensity modulator driven by a microwave signal. The intensity-modulated signal is then divided into two portions through a dense wavelength division multiplexer. One portion directly passes through the reference path while the other undergoes the transfer delay of a fiber under test (FUT). After photo-detection, two probe signals that undergo different delays are recovered and superimposed. By sweeping the microwave frequency, periodic microwave interference fringe is generated. Then, OFTD measurement is achieved by measuring the frequency of the last valley in the interference fringe. Experimental results show that a system stability of ±0.02 ps, an accuracy of ±0.07 ps, and a measurement range of at least 500 m are achieved.

The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 VDD digital logic applications. A heterojunction negative-capacitance TFET (NCTFET) has been designed using SILVACO TCAD and its accuracy demonstrated by properly fitting the simulated polarization data with calculated L-K equation solution. The prospects of the proposed structure have been manifested in the steep average subthreshold-slope of 27mV/decade over 9 decades of current and high ION/IOFF of 1016, possible due to the internal voltage amplification and voltage pinning effects. The device has been suitably implemented in inverter, ring-oscillator, 2:1 multiplexer and Full-Adder circuits and benchmarked in delay and power-consumption with a reference TFET (R-TFET) and previously proposed structures. The effect of varying thickness of ferroelectric material on the circuit-level performance has also been discussed. Furthermore, the NCTFET has been implemented in a 6-T SRAM which successfully demonstrates the effect of tFE on noise margin and read-write delay, operated at 0.4 VDD. The proposed NCTFET has been presented and justified as a promising candidate for high-speed and low power digital circuits.

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a two-stage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10−12, and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.

We demonstrate a cascaded Mach–Zehnder interferometer (MZI) based coarse wavelength division multiplexing (CWDM) (de)multiplexer on silicon-on-insulator with its spectral responses well aligned to the defined wavelength grids and are highly tolerant to the manufacturing linewidth variability. This was achieved by optimizing the waveguide widths and lengths of two arms in every MZI. As-realized CWDM (de)multiplexer exhibits a spectral shift of 0.487 nm, an insertion loss of less than 2.1 dB, and a channel crosstalk of lower than −20 dB, while reference devices fabricated on the same chips suffer from serious spectral shift of 15.4 nm to the shorter wavelength and higher insertion loss/channel crosstalk. The proposed MZI design concept can be applied to all MZI-based photonic devices and related photonic integrated circuits, so this work validates a promising design path towards practical WDM applications on silicon-on-insulator.

Suitable techniques for reading out large arrays of metallic magnetic calorimeters are very challenging and demand optimal performance in each system stage to preserve intrinsic fast signal rise time, excellent energy resolution, large energy dynamic range, and highly linear detector response. A multiplexer based on superconducting quantum interference device is the key component in achieving this goal. Linearity of the response requires a technique called flux-ramp modulation, which generates a phase-modulated complex waveform according to the sensor signal. At the end-cap of the signal processing chain it is currently recovered by a demodulation process referred to as Fourier measurement. In this letter, we prove that the mentioned method is equivalent to a maximum likelihood estimation, build an analogy to the sensor array-based direction of arrival estimation, propose an alternative approach based on the eigenvalue decomposition of a correlation matrix, present the mathematical formulation, discuss the results, and compare both methods. Our method is robust against transients due to flux ramp returning point and allows proper estimation in large phase ranges.

This letter describes a 96-Gb/s PAM-4 receiver, suitable for silicon photonics application, designed and fabricated in a 130-nm SiGe BiCMOS technology. The low-power receiver includes a TIA and a VGA, two slices of time-interleaved track and hold amplifier and two-bit folding ADC circuits, and multiplexers to deliver full-rate decoded NRZ output signals. The track and hold amplifier is based on a switched emitter–follower topology optimized for low-power operation to sample at 24 GSample/s. Half-rate PAM-4 to NRZ converters are implemented as a bandwidth-enhanced two-bit folding ADC in order to consume less power compared to flash competitors. The receiver chip consumes 545 mW, leading to an energy efficiency of 5.67 mW/Gb/s, which is one of the best among the state-of-the-art works at this data-rate.