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High-speed optical links are often used in trigger and data acquisition systems of High Energy Physics (HEP) experiments for data transfer, trigger and fast control distribution. Many experiments prefer the use of commercial off-the-shelf components (COTS) if possible, in order to avoid the non-recurrent engineering (NRE) costs and risks associated with the design of application specific integrated circuits. For the mentioned reason, static random access memory-based field programmable gate arrays (SRAM-based FPGAs) are usually deployed. However they are mostly used off-detector, where little or no radiation is present, since single event upsets in the configuration memory may alter the design functionality. In order to benefit from SRAM-based FPGAs also in radiation environments expected on-detector, suitable soft-error mitigation strategies must be adopted. In this work we evaluate the design trade-offs between performance and radiation-tolerance in a high-speed fixed-latency link based on a Virtex-5 SRAM-based FPGA. We evaluate different radiation mitigation strategies. Moreover, we experimentally verify some custom-developed placement and routing rules aimed at improving the FPGA firmware robustness against configuration upsets.

Multiple Cell Upsets (MCUs) are becoming a growing concern with the advent of the newest FPGA devices. In this paper we present a methodology suitable for analyzing the sensitivity of circuits implemented in SRAM-based FPGAs, and adopting the TMR mitigation scheme. Data about the layout of the adopted FPGA are obtained by means of laser testing. Then static analysis algorithm uses the collected data to predict the impact of MCUs on designs implemented on SRAM-based FPGAs. Thanks to this approach MCUs affecting physically adjacent cells are considered, only. We report data focusing on a Virtex-II device, showing the capabilities of the proposed method.

Flash-based FPGAs are more and more interesting for space applications because of their robustness against Single Event Upsets (SEUs) in configuration memory. However, as Single Event Effects (SEEs) are still a concern both for user memory and the configurable logic, accurate evaluations are needed to identify mitigation techniques for securing their use in space missions. In this paper the SEE sensitivity of circuits implemented in Flash-based FPGAs is evaluated with respect to the working frequency and different routing schemes. We outline different methodologies that can be used in order to characterize SEE sensitivity, using both heavy-ions radiation experiments and analytical approaches. Experimental results detail the contributions of different SEEs as a function of operating frequency and routing on a realistic circuit.

In this paper we present an analytical analysis of the fault masking capabilities of triple modular redundancy (TMR) hardening techniques in the presence of multiple cell upsets (MCUs) in the configuration memory of SRAM-based field-programmable gate arrays (FPGAs). The analytical method we developed allows an accurate study of the MCUs provoking domain crossing errors that defeat TMR. From our analysis we have found that most of the failures affect configurable logic block's routing resources. The experimental analysis has been performed on two realistic case study circuits. Experimental results are presented and discussed showing in particular that 2-bits MCUs may corrupt TMR 2.6 orders of magnitude more than single cell upsets (SCUs).

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing complex system. Unfortunately, SRAM-based FPGAs are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to successfully deploy safety- or mission-critical applications, designer need to validate the correctness of the obtained designs. In this paper we describe a system based on partial-reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs. The proposed fault-injection system uses the internal configuration capabilities that modern FPGAs offer in order to inject SEU within the configuration memory. Detailed experimental results show that the technique is orders of magnitude faster than previously proposed ones.

We introduce a new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA. The validation was performed using, for the first time, the neutron source at the RALILSIS facility. The ISlS beam features a 1/E spectrum, which is similar to the terrestrial one with an acceleration between 107 and 10 8 in the energy range 10-100 MeV. The results gathered on Xilinx SRAM-based FPGAs are discussed in terms of cross section and circuit-level modifications. © 2007 IEEE.

Hardening processor-based systems against transient faults requires new techniques able to combine high fault detection capabilities with the usual design requirements, e.g., reduced design-time, low area overhead, reduced (or null) accessibility to processor internal hardware. This paper proposes the adoption of a hybrid approach, which combines ideas from previous techniques based on software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads, to harden system based on the PowerPC 405 core available in Virtex-II Pro FPGAs. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results including comparisons with previous approaches are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory and performance overheads

The very high integration levels reached by VLSI technologies for SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced by single event upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit. When such devices are used in safety-critical applications, fault-tolerant techniques are needed to mitigate the effects of SEUs in FPGAs' configuration memory. In this paper, we analyze the effects induced by the SEUs in the configuration memory of SRAM-based FPGAs. The reported analysis outlines that SEUs in the FPGA's configuration memory are particularly critical since they are able to escape well-known fault masking techniques such as triple modular redundancy (TMR). We then present a reliability-oriented place and route algorithm that, coupled with TMR, is able to effectively mitigate the effects of the considered faults. The effectiveness of the new reliability-oriented place and route algorithm is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique

Many safety-critical applications today rely on computer-based systems in which several computing nodes communicate through a network backbone. As the complexity of the systems under analysis grows, designers must devise fault-injection models that strike a balance between two conflicting requirements: On the one hand, models should be as close as possible to a system's physical implementation to reflect precisely the effects of real faults. On the other hand, abstract, easily manageable models minimize the time required for the fault-injection experiments, letting designers analyze sets of faults wide enough to provide statistically meaningful information. In addressing this issue, we have devised a fault-injection environment to study the effects of soft errors in CAN networks. Our cosimulation environment consists of two modules. The first, a traffic generator module implemented in software, emulates the applications running in each node of the network. The second, a network backbone module implemented in hardware, simulates the activities involved in information exchange between network nodes, in compliance with the CAN protocol specification. To allow evaluation of complex workloads as well as large fault lists, we use an FPGA board to emulate the network backbone module. This enables cycle-accurate simulations of the entire network's behavior with very low speed penalties.

Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.

SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets (SEUs) that, by changing the FPGA's configuration memory, may affect dramatically the functions implemented by the device. In This work we describe a new approach for predicting SEU effects in circuits mapped on SRAM-based FPGAs that combines radiation testing with simulation. The former is used to characterize (in terms of device cross section) the technology on which the FPGA device is based, no matter which circuit it implements. The latter is used to predict the probability for a SEU to alter the expect behavior of a given circuit. By combining the two figures, we then compute the cross section of the circuit mapped on the pre-characterized device. Experimental results are presented that compare the approach we developed with a traditional one based on radiation testing only, to measure the cross section of a circuit mapped on an FPGA. The figures here reported confirm the accuracy of our approach.

Cache memories embedded in most of complex processors significantly contribute to the global single event upset-induced error rate. Three different approaches allowing the study of this contribution by fault injection are investigated in this paper.

This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.

We describe an approach for analyzing single-event transients (SETs) in combinational circuits. The approach analyzes SETs via zero-delay simulation with the same accuracy of timing simulators, but with a speedup of three orders of magnitude.

Hardware designers need effective techniques for early evaluation of the hardening mechanisms adopted in safety-critical VLSI circuits. We propose field-programmable gate-array based circuit emulation for performing fault-injection campaigns. Experimental results show that the new technique is about four orders of magnitude faster than simulation-based fault injection.

This paper deals with a software modification strategy allowing on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is therefore particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.