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Distributed simulation of circuits in which the process interactions form a cyclic graph is addressed. The method described uses a dataflow network synthesized on the basis of the connectivity of the circuit components. The algorithm, called Yaddes (which stands for yet another asynchronous distributed discrete-event simulation algorithm), computes for each component a quantity time of next event, which permits the corresponding model to execute asynchronously as far ahead in simulation time as possible. The network ensures that a simulation process executing in a distributed processing environment will not deadlock. The algorithm, which also offers acceptable performance and provable correctness, is compared with the two other principal algorithms proposed to avoid deadlocks: the deadlock recovery algorithm and the exception-mode algorithm. Performance results for Yaddes are presented. >

A three-dimensional close-packed array of Josephson junctions was successfully produced in the form of a bulk granular superconductor. The granular system is a tightly compressed solid of oxide coated small tin particles in the thousand A range. The three-dimensional array of Josephson junctions thus formed showed coherent Josephson oscillations when external rf radiation was imposed, rf induced constant voltage steps were observed on its I-V characteristics at voltages a few thousand times the Josephson voltage hv/2e. The external rf radiation also induced Stable dc voltages on unbiased bulk samples, suggesting a practical mode of microwave detection. The analogy of this bulk superconducting system with a magnetic spin system will be discussed.

The authors examine the limitations of the timing semantics in the conventional behavioral simulators and present a preemptive scheduling mechanism for accurate behavioral simulation results. They consider two signal transitions at the input ports of a component, where the second input transition arrives later than the first transition. The first and second input transitions cause first output signal transitions O/sub 1/ and O/sub 2/, respectively, to be generated at the output port of the component. When the logical values of O/sub 1/ and O/sub 2/ conflict with each other and O/sub 1/ arrives later than O/sub 2/, O/sub 1/ is preempted by O/sub 2/. In addition, an input signal to a component whose pulse duration is smaller than the inertial delay of the component, T/sub mip/, is discarded during simulation. Empirical measures for T/sub mip/ relative to the high-to-low and low-to-high propagation delays of the component for TL (transistor-transistor logic), NMOS, and CMOS technologies are presented. This approach has been implemented in the ADLIB-SABLE simulator at Stanford University. >

A new way to use Josephson junctions for parametric amplification with phase control is proposed. The dc current bias of the junction is adjusted such that the Josephson oscillation automatically synchronizes with the input signal and oscillates at twice the signal frequency with the proper relative phase. The impedance of the junction then has a negative resistive component which can be used for amplification. Extension to other phase sensitive circuits is also discussed.