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The popularity of fourth generation (4G) cellular communication technology, and the concurrent predominance of second (2G) and third generation (3G) systems have made multi-standard wireless transceivers a necessity. This paper describes the system level planning, the architectural design, and the VLSI implementation of a reconfigurable discrete-time $\Delta \Sigma $ ADC for a multi-standard 2G/3G/4G wireless receiver. We present an optimized switched-capacitor loop filter implementation that maximizes the achievable sampling rate by deploying an early regeneration of the quantizer. Reconfigurability is mainly realized at the architectural level by adapting the oversampling ratio and the quantizer resolution, depending on the mode, to achieve the required dynamic range. Implemented in a 130 nm CMOS technology, and occupying an area of 0.31 ${\hbox {mm}}^{2}$ , the modulator runs at a maximum sampling rate of 450 MHz. The ADC achieves 87 dB and 63 dB DR in a 100 kHz and 25 MHz bandwidth, respectively. The effective resolution ranges from 13.2 bit to 9.7 bit at a scalable power consumption between 3.4 mW and 56.7 mW from a single 1.2 V supply. An open loop reference buffer is embedded on-chip to generate the required reference voltage levels (without the need for external components) making the modulator suitable for fully integrated cellular transceivers.

A 4 Mb embedded phase change memory macro has been developed in a 90 nm 6-ML CMOS technology. The storage element has been integrated using 3 additional masks with respect to process baseline. The cell selector is implemented by a standard LV nMOS device, achieving a cell size of 0.29 μm2. A dual-voltage row decoder and a double-path column decoder are introduced, enabling a completely low voltage read operation. A 20b-parallelism write scheme is embedded in the digital controller in order to maximize throughput. In alternative, a power-saving low-parallelism write algorithm can be employed. The macro features a 1.2 V 12 ns read access time and a write throughput of 1 MB/s. Set and reset current distributions showing a good read window are presented and robust reliability results are demonstrated.