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We clarify the role of carbon and dysprosium in nickel-dysprosium-silicide (Ni[Dy]Si:C) contacts formed on silicon:carbon (Si1-yCy or Si:C) for Schottky-barrier height (SBH) reduction. Carbon-induced energy bandgap Eg narrowing and the segregation of dysprosium (Dy) at the Ni[Dy]Si:C/Si:C interface were shown to be responsible for SBH reduction in this paper. First, we show that electron barrier height (PhiBN) reduction of up to 69 meV (or 10.3%) for NiSi can be achieved with the scaling of substitutional carbon Csub concentration from 0% to 1.0%. Second, new evidence revealing the segregation of Dy-based interlayer at the Ni[Dy]Si:C/Si:C interface and an additional 321 meV (or 53%) reduction in PhiBN for NiSi:C are presented. This could be due to charge transfer at the Ni[Dy]Si:C/Si:C interface. The successful modulation of PhiBN for Ni[Dy]S:C translates to an effective 41% reduction in device REXT , resulting in improved drive current performance. This opens new avenues to optimize the Si1-yCy contact interface for extending transistor performance in future technological generations.

We report the demonstration of strained p-channel multiple-gate transistors or FinFETs with a novel liner-stressor material comprising diamond-like carbon (DLC). In this work, a DLC film with very high intrinsic compressive stress up to 6 GPa was employed. For FinFET devices having a 20 nm thin DLC liner stressor, more than 30% enhancement in saturation drain current IDsat is observed over FinFETs without a DLC liner. The performance enhancement is attributed to the coupling of compressive stress from the DLC liner to the channel, leading to hole mobility improvement. Due to its extremely high intrinsic stress value, significant IDsat enhancement is observed even when the thickness of the DLC film deposited is less than 40 nm. The DLC liner stressor is a promising stressor material for performance enhancement of p-channel transistors in future technology nodes.

We report the first investigation of the impact of diamond-like carbon (DLC) high-stress liner on strained p-channel metal-oxide-semiconductor field-effect transistors (p-FETs) having silicon-germanium (SiGe) source-and-drain (S/D) stressor. The DLC exhibited a very high compressive stress of ~ 5 GPa. At a fixed I off of 1 x 10-7 A/mum, the DLC liner stressor contributed to a further 11% I on enhancement for p-FETs with Si0.75Ge0.25 S/D. This is the first demonstration that further boost in device performance in a p-FET that is already strained using Si0.75Ge0.25 S/D can be achieved with DLC liner stressor. Due to the extremely high intrinsic compressive stress of the DLC, a very small DLC thickness of ~ 27 nm is sufficient for achieving significant strain effect and performance enhancement.

We report the first demonstration of pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm. Ge S/D compressively strains the channel to provide up to ~ 100% I Dsat enhancement. We also introduce a novel Melt-Enhanced Dopant diffusion and activation technique to form fully embedded Si0.15Ge0.85 S/D stressors in nanowire FETs, further boosting the channel strain and achieving ~ 125% I Dsat enhancement.

We report the integration of nickel platinum germanosilicide (Ni1-yPtySiGe) contacts in tri-gate FinFETs with silicon germanium source/drain stressors for enhanced drive current performance. The structural and electrical properties of Ni1-yPtySiGe contacts with platinum (Pt) concentrations up to 20 atomic % (at. %) were explored for FinFET integration. Our results show that Ni1-yPtySiGe incorporated with 10 at. % Pt shows superior morphological stability, a suitably low sheet resistivity and the lowest Schottky hole barrier height (PhiP B) among the candidates evaluated. The low PhiP B(0.309 eV) provides a 15% reduction in series resistance Rseries. With a superior morphological stability and reduced Rseries, FinFETs integrated with contacts exhibit an overall 18% improvement in drive current compared to FinFETs with NiSiGe contacts.

In this letter, we report the impact of incorporating aluminum (Al) in nickel aluminide disilcide (NiSi2 -xAIx) on the Schottky-barrier for electrons (PhiB n) in NiSi2-xAlx/Si contacts for parasitic series resistance reduction. A wide range of Al concentration was investigated, and an optimum value was obtained. Based on the optimum Al concentration, arsenic- segregated NiSi2-xAlx (As-segregated NiSi2-xAlx) contacts were shown to achieve conduction band-edge Schottky-barrier heights with PhiB n = 0.133 eV. This novel As-segregated NiSi2-xAlx contact was integrated in FinFETs with a gate length of 80 nm and a fin width (WFin) of 11 nm, demonstrating improvement in current drivability of 30% over FinFETs with As-segregated NiSi contacts. We show that these ultranarrow fins (WFin = 11 nm) can be fully silicided reliably with NiSi2-xAlx, demonstrating scalability and the smallest fully silicided Si fins reported to date. For these ultra-narrow Si fins, we have successfully alleviated the concerns of parasitic series resistance without the use of selective epitaxial raised source and drain technology.

To explore the potential of nickel-silicide:carbon (NiSi:C) as contact technology for MOSFETs with silicon-carbon (Si:C) source/drain (S/D) regions, we examined the effects of incorporating 1.0 at.% of carbon in Si prior to nickel silicidation. The addition of carbon was found to improve the morphological and phase stability of NiSi:C contacts. This is possibly due to the presence of carbon at the NiSi:C grain boundaries and NiSi:C/Si interface, which will modify the grain-boundary and interfacial energies. This will influence the kinetics of NiSi:C silicidation. In this letter, we have also demonstrated the first integration of NiSi:C contacts in MOSFETs with Si:C S/D regions. We further show that NiSi:C silicidation suppresses the formation of active deep-level defects, leading to superior n+/p junction characteristics.

The performance of n-channel (110)-sidewall trigate fin-shaped field-effect transistors (FinFETs) is seriously compromised as (110) surfaces have significantly lower electron mobility than (100) surfaces. Straining the channel in (110)-sidewall FinFETs using lattice-mismatched silicon-carbon (Si1-yCy) stressors alone was experimentally determined to be far less effective than doing the same with (100)-sidewall FinFETs. By additionally incorporating a tensile silicon nitride contact etch-stop layer, the increase in longitudinal tensile stress and the introduction of vertical compressive stress result in significant further IDsat enhancement, highlighting the importance of the vertical compressive stress component for enhancing (110)-sidewall FinFET performance.

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.

We have fabricated n-channel 25-nm gate length FinFETs with Schottky-barrier source and drain featuring a self-aligned ytterbium silicide (YbSi1.8). A low-temperature silicidation process was developed for the formation of the low electron barrier height YbSi 1.8 phase, without reaction with SiO2 isolation or SiN spacer materials, enabling integration in a CMOS fabrication process flow. The fabricated device exhibits good device characteristics with a drive current of 241 muA/mum at VDS=VGS-Vt=1 V, Ion/Ioff=104 at VDS=1.1 V, subthreshold swing of 125 mV/decade, and drain-induced barrier lowering of 0.26 V/V

Negative bias temperature instability (NBTI) characteristics of p-channel field-effect transistors (p-FETs) with diamond-like carbon (DLC) liner stressor having ultrahigh compressive stress (~ 5 GPa) are investigated for the first time. Ultrafast measurement was employed for NBTI study. Power law slopes ranging from ~ 0.058 to ~ 0.072 are reported here. P-FETs with higher channel strain show greater threshold voltage shift (DeltaVth) and transconductance degradation than those with lower or no channel strain under the same NBT stress condition Vstress. Strained p-FETs with Si S/D and DLC stressors are projected to have an NBTI lifetime of ten years at VG = -0.99 V using Eox power law lifetime extrapolation model or at VG = -0.76 V using the exponential Vstress model.

In this letter, sulfur (S) segregation was exploited to attain a record-low electron barrier height (PhiB N) of 110 meV for platinum-based silicide contacts. Sulfur-incorporated PtSi:C/Si:C contacts were also demonstrated in strained FinFETs with Si:C source/drain stressors. Incorporation of sulfur at the PtSi:C/Si:C interface in the source/drain regions of FinFETs provides a 51% improvement in external resistances and a 45% enhancement in drive current as compared to devices without S segregation. The remarkable reduction in PhiB N is explained using charge transfer and dipole formation at the silicide/semiconductor interface with S segregation.

This letter reports the first demonstration of the integration of nickel-silicide (NiSi) source/drain (S/D) contact technology with a novel aluminum (Al) segregation at the NiSi/p +-Si interface in the S/D of p-channel FinFETs to reduce contact resistance. This leads to reduction in parasitic series resistance. We show that the addition of a low-dose (2times1014 atom/cm2) Al ion implant step in the Si S/D of p-channel FinFETs could achieve ~ 19% enhancement in drive current. This is attributed to the reduction in effective Schottky barrier height of holes at NiSi/p+-Si interface, from ~ 0.4 to ~ 0.12 eV, using Al segregation.

We report the first demonstration of a p-channel multiple-gate (trigate) FinFET with a liner stressor comprising diamond-like carbon (DLC) film. We also report on the detailed process that enables the adhesion of DLC with ultrahigh compressive stress on the three-dimension topology of the FinFET structure. The intrinsic compressive stress for the DLC film is 6 GPa, the highest ever reported for a liner stressor formed over a multiple-gate device structure or FinFET. A high stress-thickness product was successfully realized without film delamination. This leads to a very significant drive current boost for the FinFET with DLC liner stressor as compared to a control FinFET without the DLC liner.

Pure germanium (Ge) source and drain (S/D) stressors are integrated with ultrathin-body (UTB) and nanowire field-effect transistors (FETs). This is the first report of the integration of Ge S/D stressors in FETs. The Ge S/D stressors induce a large compressive stress in the channel, resulting in up to 80% IDsat enhancement in UTB-FETs. Electrical results further show that increased substrate compliance effects allow nanowire FETs to achieve even higher levels (96%) of strain-induced enhancement.

We report the integration of a new liner stressor comprising diamond-like carbon (DLC) film over a p-channel transistor. A high compressive stress of 6.5 GPa was achieved in a high-stress film with a thickness of 27 nm. A 74% enhancement in drive current was observed for the strained device with DLC liner as compared to a control device without DLC liner. Due to its much higher intrinsic stress value compared to conventional SiN films, a thinner DLC layer can induce comparable amount of stress in the transistor channel compared to a thicker SiN. The DLC material is a potential next-generation high-stress and low-permittivity liner stressor material suitable for application in transistors with aggressively scaled pitch dimensions.

A novel and low-cost spacer removal technique proved successful in further enhancing the IDsat performance of already strained n-channel trigate FinFETs with SiC source and drain (S/D) stressors. This extra enhancement is attributed to increased longitudinal tensile channel stress as a result of increased stress coupling efficiency from the SiC S/D stressors to the channel. The electrical results also establish that this extra enhancement will become even more significant as physical gate lengths are scaled down.

A novel and simple process for the exploitation of metal-gate-induced stress in the Si channel region of a FinFET is reported. TaN metal-gate electrode was employed. The use of a silicon nitride capping layer, which covered the metal gate during the source and drain anneal, led to a large stress being developed as a result of the thermal-expansion coefficient mismatch between the gate and the capping layer. The resulting strain was retained and transferred to the Si channel. The stress introduced by the gate stressor was found to enhance the performance of the n-channel FinFETs and is believed to be tensile in the source-to-drain direction. This approach may be applicable to other metal-gate materials having a mismatch in the thermal-expansion coefficient with surrounding capping materials