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This paper presents a high-performance radio frequency (RF) power amplifier (PA) module for which an optimum chip-level packaging structure is proposed to reduce the operating temperature of the RF PA monolithic microwave integrated circuit (MMIC). Because the output power (Pout) and the efficiency of a RF PA module are strongly affected by the thermal characteristics of the PA MMIC, various types of heat spreader materials and thermal interface materials have been examined to implement the PA chip-level packaging structure, and the optimum combination is proposed for a performance enhancement of the PA module in this paper. In addition, the optimum form-factor of the heat spreader was suggested based on a thermal simulation. To verify the proposed PA chip-level packaging structure, a 10 W 618 GHz RF PA MMIC using a commercial 0.25-m gallium nitride high electron mobility transistor process was designed and implemented for radar applications. The operating temperature of the PA MMIC on the proposed chip-level packaging structure shows a dramatic reduction of 24.8 C, and accordingly, the average Pout and average power-added efficiency are enhanced by up to 9.2% and 2.8%, respectively, when compared with a PA module using the conventional chip-level packaging structure.

In this paper, a switchless dual-band, dual-mode power amplifier (PA) has been developed for multioctave operation. For the switchless dual-band operation, we proposed a new coupled-line-based diplexer structure. The proposed diplexer operates as a balun at high-band frequencies and the coupled line at low-band frequencies. To better understand the proposed diplexer structure, a detailed analysis is performed based on a coupled-line theory. The interstage and output-stage matching networks of the PA are designed by using the proposed diplexer. To maximize the power-added efficiency (PAE) of the designed PA, turn off the unused band PAs and decide the optimum off-state bias condition of transistors. The designed dual-band, dual-mode PA is fabricated with commercial 0.25- $\mu \text{m}$ GaN HEMT process. The fabricated PA shows over 15-dB small-signal gain at 5–11 GHz in the low-band mode and 9–18 GHz in the high-band mode. The measured average output power and PAE are 35 dBm, 23% in the low-band mode and 37 dBm, 26% in the high-band mode.

Two-stage reactively matched gain cells are proposed to implement a high-gain multioctave distributed power amplifier (DPA). The proposed reactively matched distributed amplifier (RMDA) structure shows high gain and power in a small die size. Detailed analysis is presented to understand the design criteria for interstage matching of reactively matched cells. A shared dc bias network is proposed to simplify the biasing of each section to reduce the DPA die size. The thermal coupling effect of GaN high-power amplifier is minimized by optimizing the chip layout. The theoretical analysis is verified by the simulation and supported by the measured data. Two RMDAs are fabricated with a commercial 0.25- $\mu \text{m}$ GaN HEMT process. The implemented RMDA with the compact transistor layout has been implemented in a small die size of 10.7 mm2 and shows output powers reaching 40.3–43.9 dBm, power added efficiencies (PAEs) of 16–27%, and small-signal gains of 15.3–23.2 dB. The RMDA with the reduced thermal coupling achieves 40.6–43.4 dBm with a peak PAE of 29% in a slightly larger die size of 13.8 mm2. To the best of our knowledge, this is the first demonstration of a GaN DPA using reactively matched gain cells, showing very high gain and efficiency over multioctave bandwidth in a small die size.

In this paper, a quantitative analysis to obtain the equivalent circuit parameters of helix-on-pads (HoPs) is presented. To simplify the analysis, the HoP, which is a kind of helical wires vertically mounted on a dielectric substrate, is subdivided into two parts using the split-up method based on field distribution. The analysis derives RLGC formulas of the HoPs for various dimensions and number of loops. To verify the accuracy of the derived RLGC model, electromagnetic (EM) simulations for various HoPs cases are also performed. The EM-simulated results show a good agreement with the calculated results. To experimentally demonstrate the analysis and usefulness of the HoP, two HoPs are designed and fabricated for W-CDMA dual-band (Band-2 and Band-5) handset power amplifier (PA) applications. Measured RF performances of the standalone HoPs and composite PA show good agreements with the calculated results, thus validating the usefulness of the analysis and design.

A novel extraction method to estimate the thermal resistance ( $R_{\mathrm {th}})$ of a multifinger GaAs heterojunction bipolar transistor (HBT) device is presented based on the simplified Fourier’s law. By calculating the thermal coupling resistance between the fingers on top of the self-heating thermal resistance, the values of $R_{\mathrm {th}}$ of multifinger devices for various dimensions are accurately calculated while maintaining the simplicity of calculation. To verify the idea, the proposed method is compared with the measurement-based method as well as the analytic methods, such as the finite-element method and the solution of 3-D Laplace’s equation. For four-finger HBT devices, the extracted $R_{\mathrm {th}}$ results showed good agreements with the analytic methods within an error of 9% and the measurement-based results with a deviation of 7.4%, thus convincing the usefulness of the proposed method.

In this paper, an analytical formula for the net gain of single-input single-output single frequency network (SISO-SFN) is derived. In order to formulate the net SISO-SFN gain (SISO-SFNG), we derive the average signal to noise ratio, where the SFN gain is calculated by the aggregate power sum as a function of the power imbalance, whereas the SFN loss is calculated by a two-term exponential model from a curve fitting as a function of the erasure probability, modulation order, and code rate. The accuracy and effectiveness of the derived formula are verified by comparing the measurement results with the analytical results. The derived formula helps to rationalize why the net gain is positive or negative under a given condition, e.g., a negative net gain is obtained if the power imbalance exceeds the erasure-free limit. The formula would be very useful to predict more realistic and accurate service coverage of SISO-SFN for various system configurations.

A novel coupler/reflection-type electronic impedance tuner is proposed with quantitative analysis. The tuner is divided into a magnitude part and a phase part, and the magnitude and phase of the tuner impedance can be controlled separately just with one design parameter, respectively, thus facilitating programmable control for constant magnitude and uniform phase distribution. The tuner with standing wave ratio $({\rm SWR}) = {2.5}$ and 6 was implemented for 3G/4G handset low-band transmitter (Tx) power amplifier (PA) load-pull measurement. The fabricated tuner showed very uniform reflection coefficient distribution with magnitude deviations of less than 0.05/0.08 at ${\rm SWR}= 2.5 / 6$ and phase deviations of less than 5 $^{\circ}$ . PA load-pull measurement result using the tuner showed good agreement with a mechanical tuner, thus verifying the practical usefulness of the proposed tuner.

Fully-integrated multi-mode multi-band (MMMB) reconfigurable power amplifier (PA) is implemented using single PA-cores for high- and low-frequency bands, respectively. This PA has five output paths and covers quad-band Gaussian Minimum Shift Keying/Enhanced Data Rates for Global Evolution and penta-band Universal Mobile Telecommunications System/Long Term Evolution mode operation with band combination in a small form-factor. To optimize the PA, the proposed structure reconfigures the PA-core cells as well as the interstage/output matching network. When compared with the single-mode single-band dedicated PAs, the fabricated PA showed comparable RF performance for all modes and bands, except for PAE degradations of 3.1% and 1.9% for high- and low-band, respectively, thus validating the usefulness of the proposed structure for MMMB PA applications.

In the digital television (DTV) broadcasting system, high power amplifier (HPA) is the most essential device to expand the service availability and coverage. However, as the input power level of HPA increases, the HPA is driven into the saturation mode and HPA output signal suffers nonlinear distortion. HPA nonlinearity is potentially responsible for adjacent channel interference and inter-symbol interference (ISI). To prevent these negative effects, digital pre-distortion (DPD) is one of the most widely used techniques for the HPA linearization. In order to estimate the HPA nonlinearity, DPD technique requires a feedback signal, which needs to be appropriately down converted and digitized from HPA output. However, since the feedback signal might be generally influenced by offset error, it is important to reduce the offset error in order to improve HPA linearization. In this paper, an adaptive DPD technique based on iterative look-up table (LUT) update and adaptive acquisition is proposed. The proposed DPD technique is validated on the advanced television systems committee (ATSC) terrestrial DTV broadcasting system by computer simulation and laboratory test.

A high-performance V-band cascode HEMT mixer is presented together with a compact downconverter module integrating the mixer with other receiver MMICs. The cascode mixer was optimized for conversion gain and/or linearity by employing the low-pass interstage networks and by optimizing the bias voltages. The low-pass interstage network effectively filters out the unwanted harmonics and spurious signals, and therefore, enhances the gain and the linearity of the cascode mixer. On a two-tone test, the cascode mixer showed a high conversion gain of 6.3 dB with an LO power of 2.6 dBm at 60 GHz. When the gate bias to the upper common-gate HEMT was tuned for the intermodulation distortion "sweet spot" theoretically predicted by the authors , the mixer showed a high third-order intercept point of 11.2 dBm with a decent gain of 4.1 dB under a small DC power consumption of 8 mW. To benchmark the performance of the cascode mixer of this work, a waveguide-based compact V-band downconverter module was built by integrating the mixer with an MMIC LNA, a VCO, and a LO driving amplifier. The downconverter module showed a conversion gain higher than 20 dB from 57.5 to 61.7 GHz. This paper shows the potential of the cascode FET mixer for high-performance compact downconverter applications at millimeter-wave frequencies.

A MMIC-compatible miniaturized "active" predistorter using cascode FET structures is presented. The predistorter has added functionality of gain, as well as programmable gain and phase variation characteristics, which are required to compensate or the nonlinear distortion of a wide range of power amplifiers (PAs). Thanks to the inherent gain of the predistorter, a need for an additional buffer amplifier is eliminated. Furthermore, it can eventually replace the first-stage amplifier in the multistage PAs, making this approach well suited to MMIC implementation. A simple analysis is performed to understand the phase variation mechanisms in the proposed predistorter and to identify the dominant sources of phase variation. To demonstrate the general usefulness of this predistorter, the cascode predistorter was applied to linearize watt-level MMIC amplifiers for CDMA handset applications, as well as 30 W high power amplifiers for base-station applications. Adjacent channel power ratio (ACPR) improvement of 3-5 dB was achieved with off-chip predistorter when applied to 0.9 W monolithic amplifiers. The predistorter was also integrated with a 1.6 W MMIC PA on a single chip, replacing the first-stage transistor of the amplifier.

Ultra small-size power amplifier (PA) modules were developed for WCDMA handset applications. To reduce the size of the PA modules, the bulky transmission lines and lumped surface mountable chip elements of the conventional output matching network (OMN) were replaced with the proposed helix-on-pad (HoP) and an integrated passive device (iPD), respectively. Three 2 mm times 2 mm single-band PA modules were developed using the proposed OMNs for UMTS Band-5, Band-1, and Band-2 applications. No RF performance degradation was observed from the size-reduced PA modules. For the demonstration of ultimate size reduction, a dual-band PA for UMTS Band-2/ Band-5 application was developed in a 3 mm X 3 mm form-factor. The PAs exhibited adjacent channel leakage ratios (ACLRs) better than -38 dBc over the entire output power range together with power-added efficiencies (PAEs) in excess of 39 % at 28.5 dBm. Besides, the PAs showed good low-power efficiency of 16% at Pout = 16 dBm due to the stage-bypass architecture. The proposed method can be applied in a variety of wireless Tx applications requiring small form-factors and high efficiencies.