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This article presents 16-times frequency multiplier composing of two four-times frequency multipliers (quadrupler) in cascade connection. The proposed topology is new structure of tuned-frequency multiplier (TFM) for better harmonic rejection ratio (HRR) with wide frequency range and low power consumption. For accomplishing reliable output frequency band of 16–28 GHz, the whole band is divided into 64 subsidiary frequency bands by applying 6-bits digitally controlled capacitor-bank of LC -tuned tank. The proposed quadrupler is consisted of a harmonic generator (HG) and a cascode LC -tuned buffer. The proposed HG topology is based on double balanced mixer (DBM). Unlike typical mixer bias, the bottom differential pair devices of the proposed HG are C-class biased to generate more desired the fourth order harmonic. In addition, to reduce power consumption and frequency conversion gain variations for the whole target frequency band, negative- $g_{m}$ differential pair is added in parallel to enhance the equivalent parasitic parallel resistance of the HG LC -tank while keep it from oscillation. Great efforts have been contributed to minimize process variation effects by simple but relatively accurate capacitance calibration. Furthermore, each LC -tuned tank output amplitude is regulated by a loop to maintain same output swing for the best optimization of specifications such as power consumption and HRR. The proposed 16-times multiplier is fabricated on 65-nm complementary metal–oxide–semiconductor (CMOS) process and successfully tested. Chip die size 0.7 mm2 excluding input/output (I/O) pads and average power consumption is only 6 mW for 16–28 GHz frequency band. Also, negligible phase noise degradation is achieved.

Spatial thermal distribution of a chip is an essential information for dynamic thermal management. To get a rich thermal map, the sensor area is required to be reduced radically. However, squeezing the sensor size is about to face its physical limitation. In this background, we propose an area-efficient thermal sensing technique: hybrid temperature sensor network. The proposed sensor architecture fully exploits the spatial low-pass filtering effect of thermal systems, which implies that most of the thermal information resides in very low spatial frequency region. Our on-chip sensor network consists of a small number of accurate thermal sensors and a large number of tiny relative thermal sensors, responsible for low and high spatial frequency thermal information respectively. By combining these sensor readouts, a thermal map upsampler synthesizes a higher spatial resolution thermal map with a proposed guided upsampling algorithm.

In this paper, a unified media application processor (UMAP) is presented for 2D/3D image analysis/synthesis applications on handheld devices. UMAP integrates parallel and sequential processing layers which consist of heterogeneous functional IPs for general media contents processing on today's application processors (AP). Based on the heterogeneous many-core platform, UMAP supports not only graphics and vision processing for real-time augmented reality (AR) but also disparity estimation and 3D display synthesis for 3D-view AR acceleration. A new concept of 3D-view AR which synthesizes 3D display contents from two vertically aligned stereo images and a self-constructed disparity map is introduced to achieve true realism for next generation mobile devices. For low-cost 3D-view AR processing, a homography-based disparity estimation (HDE) algorithm is proposed to construct a disparity map between two stereo images with small implementation overhead. For real-time and energy-efficient system organization, workload-balanced 3-stage pipelined architecture and a mixed-mode feature extraction engine (FEE) are also implemented in UMAP. The 3-stage pipelined system which consists of graphics, vision, and display operation stages reduces per-frame execution latency, while dynamic analog/digital mode reconfiguration based on mixed-mode FEE reduces per-frame energy dissipation, so real-time energy-efficient 3D-view AR can be realized in UMAP. FEE performs high-speed corner detection for vision processing based on four pairs of analog current contention logics (CCLs). Especially, a diode-connected current sensing stabilizer (CSS) in each CCL reduces minimum sensing current for corner detection, so average power consumed in CCL is reduced by 44.9%. In 2D or 3D-view AR processing, FEE with four CCLs replaces the parallel processing core cluster which is the most power hungry IP in UMAP, so 96.7% of cluster power and 99.1% of target detection time are saved in real operation. Based on the 3-stage pipelined architecture with the dynamic mode reconfiguration technique, the entire UMAP achieves up to 64.4% of energy reduction compared to the previous state-of-the-art media processors in full operation.

A pattern-matching based image recognition accelerator (PRA) is presented for embedded vision applications. It is a hardware accelerator that performs interest point detection and matching for image-based recognition applications in real time in both mobile devices and vehicles. The proposed system is implemented as a small IP, and it has eight times higher throughput than state-of-the-art object recognition processors, which are implemented based on a heterogeneous many-core system. PRA has three key features: 1) joint algorithm–architecture optimizations for exploiting bit-level parallelism; 2) a low-power unified hardware platform for interest point detection and matching; and 3) scalable hardware architecture. PRA achieves $9.5\times$ performance improvement with only 30% of logic gates including static random-access memory (SRAM) compared to the state-of-the-art object recognition processors. It consists of 78.3 k logic gates and 128 kB SRAM, which are integrated in a test chip implemented for PRA verification. It achieves 94.3 frames per second (fps) in 1080 p full HD resolution at 200-MHz operating frequency while consuming 182 mW. Each complete operation for interest point detection and matching requires 2.09 cycles and 8 cycles on average, respectively, based on a unified bit-level matching accelerator, which is implemented only with 680 logic gates.

We embed special function units (SFUs) in homogeneous stream processors (SPs) within a graphics processing unit (GPU), to improve its performance in running modern programmable shaders, which make poor use of a single-instruction multiple-data (SIMD) architecture. We also compact instructions, so as to reduce the size of the instruction memory, and reduce area requirements by using a partial SFU in SPs, and a lookup table which is shared between multiple SFUs. The result is an increase of 88% in utilization and a reduction in the normalized area-delay product of 27%, compared to a baseline SIMD architecture. We verified our architecture on an field-programmable gate-array evaluation platform with an ARM9 host processor and a full 3-D graphics pipeline.

This paper presents a heterogeneous multimedia processor for embedded media applications such as image processing, vision, 3-D graphics and augmented reality (AR), assuming integrated circuit (IC)-stacking on Si-interposer. This processor embeds reconfigurable output drivers for external memory interface to increase memory bandwidth even in a mobile environment. The implemented output driver reconfigures its driving strength according to channel loss between the implemented processor and the memory, so it enables highspeed data communication while achieving 8× higher memory bandwidth compared to previous embedded media processors. The implemented processor includes three main programmable intellectual properties, mode-configurable vector processing units (MCVPUs), a unified filtering unit (UFU), and a unified shader. MCVPUs have 32 integer (16 bit) cores in order to support dual-mode operations between image-level processing and graphics processing. This mode-configuration enables a frame-level pipelining in AR application, so the proposed processor achieves 1.7× higher frame rate compared to the sequential AR processing. UFU supports 16 types of filtering operations only with a single instruction. Most image-level processing consists of various types of filtering operations, so UFU can improve media processing performance and energy-efficiency. UFU also supports texture filtering which is performance bottleneck of common graphics pipeline. A memory-access-efficient (off-chip memory) texturing algorithm named as an adaptive block selection is proposed to enhance texturing performance in 3-D graphics pipeline. UFU has two-level on-chip memory hierarchies, a 512B level-0 (L0) data buffer, and an 8kB level-1 (L1) static random-access memory (SRAM) cache. The small-sized L0 data buffer limits direct references to the large-sized L1 SRAM cache to reduce energy consumed in on-chip memories. Unified shader consists of four homogeneous scalar processing elements (SPEs) for geometry operations in 3-D graphics. Each SPE has single-precision floating-point data-paths, since precision of geometry operations in 3-D graphics is important in today's handheld devices (high resolution). The proposed media processor is fabricated in 0.13 μm CMOS technology with 4 mm × 4 mm chip size, and dissipates 275 mW for full AR operation.

In this paper, sensitivity analysis and Taguchi's method are applied to the design of dual band patch antenna using gap coupling. The proposed structure uses T-slotted aperture coupling between patch and feed line of ground plane. Using sensitivity analysis, optimum dimensions of patch and coplanar waveguide (CPW) feed line are first sought. Then the optimized values are modified by Taguchi's method in order to obtain robustness against the change of material constant and gap between patch and feed line. Moreover, the validity of the robust design has been tested with two antennas manufactured according to the final design. From the numerical and experimental results, it is confirmed that the final design is insensitive to noise factors.

This paper introduces an interrogation enhancer (IE) as an external system that boosts a reader continuous wave (CW) with its auxiliary CW. The boosted reader CW powers the backscatters from a passive ultrahigh frequency radio frequency identification (UHF RFID) tag to reach the reader in extended range. The system performance is verified according to the measured ranges in practical tests. The IE permits the reader to successfully interrogate the tag in tripled or doubled range (e.g., 80-290 and 182-370 cm). The measurement results imply that the IE can be used for readers that may not transmit enough CW due to the local regulation or its limited battery capacity.

This paper shows applied sensitivity analysis for easier design and practical application of a planar half-wavelength low-pass filter (LPF) using defected ground structure (DGS). Typically, it is difficult to deploy planar half-wavelength low-pass filters when high power durability is required because of the very narrow line-widths of high impedance transmission line. Here, we propose a new configuration for the high impedance microstrip line using DGS structure to allow broader line width and high power handling capability. The sensitivity of the scattering parameters was calculated using the self-adjoint sensitivity formula in order to determine the proposed filter's dimension. The paper also highlights the validity of the proposed LPF optimization with its measured performance.

In this paper, we introduce a differential Colpitts voltage-controlled oscillator (VCO), performing a signal oscillation with low phase noise. The proposed VCO is a part of our RF integrated circuit (IC) transceiver design project; some transceiver components are also introduced. VCO performance is verified both in simulation and practical measurement using the proposed RF IC transceiver, communicating with a commercial passive UHF RF identification tag in a small-scale area. The measured phase-noise level at the frequency divider output port is nearly -106 and -135 dBc/Hz at 40-kHz and 1-MHz offset, respectively. A good figure-of-merit of 1.93 dB is obtained. The paper also highlights some important components [e.g., phase-locked loop, low-noise amplifier, dc offset canceller (DCOC)], and their performance. We configure the reader system, which consists of the proposed transceiver on board and a patch antenna, to use frequency hopping in 15 channels at a 200-kHz interval. The transceiver power amplifier supports 22 dBm of power. Configuring the interrogation range to 1 m, we measure received backscatters at the DCOC output port (the regenerated tag data level is 8 mV). Finally, we verify satisfactory states of the tag data process in the receiver.

This paper demonstrates new systematic approaches to equivalent circuit model extraction for defected ground structure (DGS) directly from full-wave frequency domain simulation. The DGS circuits being modeled may be either lossy or lossless. Adaptive frequency sampling (AFS) is used to minimize the computational effort of electromagnetic (EM) simulation while critically assisting in determining the cutoff frequency and attenuation pole location of the DGS circuits. A simple circuit model for lossy DGS circuits without any optimization of lumped element component values is presented. Furthermore, lossless circuit model relative complex along with a determined starting point of optimization of lumped element values is also presented in detail. The overall results are an efficient and accurate means to produce the complete equivalent models of DGS circuit for the design of various RF and microwave circuits such as oscillators that may require the high accurate nonlinear design procedures.

In this paper, a novel three-pole coupled-line bandpass filter with a microstrip configuration is presented. Presented bandpass filters use defected ground structure (DGS) sections to simultaneously realize a resonator and an inverter. The proposed coupled-line bandpass filter provides compact size with low insertion-loss characteristic. Furthermore, a DGS shape for a microstrip line is newly proposed. The proposed DGS unit structure has a resonance characteristic in some frequency band. The proposed coupled-line filter can provide attenuation poles for wide stopband characteristic due to resonance characteristic of DGS. The equivalent circuit for the proposed DGS unit section is described. The equivalent-circuit parameters for DGS are extracted by using a three-dimensional finite-element-method calculation and simple circuit analysis method. A design method for the proposed coupled-line filter is derived based on coupled-line filter theory and the equivalent circuit of the DGS. The experimental results show excellent agreements with theoretical simulation results.

A new defected ground structure (DGS) for the microstrip line is proposed in this paper. The proposed DGS unit structure can provide the bandgap characteristic in some frequency bands with only one or more unit lattices. The equivalent circuit for the proposed defected ground unit structure is derived by means of three-dimensional field analysis methods. The equivalent-circuit parameters are extracted by using a simple circuit analysis method. By employing the extracted parameters and circuit analysis theory, the bandgap effect for the provided defected ground unit structure can be explained. By using the derived and extracted equivalent circuit and parameters, the low-pass filters are designed and implemented. The experimental results show excellent agreement with theoretical results and the validity of the modeling method for the proposed defected ground unit structure.

This paper presents an analysis and design method based on finite-difference time-domain diakoptics. A complex structure is divided into several smaller subsections. The characteristics of the subsections are analyzed entirely in the time domain using mode-type discrete time-domain Green's functions. A multimode parallel algorithm is proposed to connect the subsections. Several filter analysis and design examples are presented. The effectiveness and accuracy of this method is demonstrated by comparison with other computational methods and measurements.

A transmitter (TX) leakage cancellation scheme using a micro controller (MCU) is introduced. This letter highlights an adaptive anti-leakage signal generation via an MCU, which plays the key role in reducing the TX leakage signal level. High transmitter-to-receiver (TX-to-RX) isolation is verified with measurement results.

This letter presents a new technique to reduce the size of microwave amplifiers using a defected ground structure (DGS). The DGS on the ground plane of a microstrip line provides an additional effective inductive component, which enables a microstrip line with very high impedance to be realized and shows slow-wave characteristics. The resultant electrical length of the microstrip line with DGS is longer than that of a conventional line for the same physical length. Therefore, the microstrip line with DGS can be shortened in order to maintain the same electrical length, matching, and performances of the basic (original) amplifier. To confirm the validity of this idea, two amplifiers, one of which is designed using a conventional microstrip line and the other is reduced using DGS, are fabricated, measured, and compared. The performance of the reduced amplifier with DGS is quite similar to that of the basic amplifier, even though the series microstrip lines with DGS are much smaller than those of the basic amplifier by 53.8% and 55.6% at input and output matching networks, respectively.

A new technique to reduce the phase noise in microwave oscillators is developed using the resonant characteristic of the defected ground structure (DGS). Two kinds of oscillators have been designed and measured for the examination of the reduction of phase noise by the DGS. The first adopts the DGS section under the microstrip line at the gate circuit, while the second has only the conventional microstrip line. Measurement shows reduced phase noise by 10-15 dB in the oscillator with the DGS compared to the conventional one.

In this paper, a unified interest-point detection and matching hardware with an optimized memory architecture is proposed for a real-time stereo-matching system. In order to support a stereo-matching algorithm, the unified datapath in the hardware performs not only interest-point detection and matching algorithms such as features from the accelerated segment test (FAST) and binary robust independent elementary feature (BRIEF) in real time but also a census transform, which is widely used in stereo matching. To achieve maximum performance, we propose two special memory architectures: 1) reconfigurable image memory (RIM) and 2) point cloud index memory system (PCIM). RIM is a unified memory architecture that loads pixel values from a raw image patch. Since FAST, BRIEF, and the census transform have different and complex memory access patterns, the miss rate of the memory access may increase. To optimize the memory operation, RIM can change its memory configuration according to the algorithm. PCIM is a dedicated memory system that utilizes the geometric information of the cameras in order to reduce the off-chip memory bandwidth. Based on the geometric information, PCIM removes most of the redundant candidates. Since PCIM minimizes the off-chip memory bandwidth using a dedicated cache, the performance degradation is negligible compared with the exact-nearest-neighbor method. Area-based stereo matching is accelerated based on the general-purpose computing on graphics processing units (GPGPU) architecture because the search range is adaptively reduced according to the disparity of the matched correspondences. The overall hardware consists of 1.20-M logic gates and consumes a maximum of 185 mW. Interest point detection and matching accelerator achieves 106 frames/s in 1080p full high-definition video (HD) resolution at a 200-MHz operating frequency with 3500 descriptors per image.