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A real-time high-performance transmission bandwidth-aware (TB-aware) coding bit-rate (CBR) controller design with low power consumption and low hardware complexity is presented in this article for H.265/high-efficiency video coding (HEVC) in a multiprocessor system-on-chip (MPSoC). Previous TB-aware motion estimation designs with CBR-control capability in video coding have focused on algorithm development with precise CBR models, which require a complicated algorithmic derivation according to the system on-demand CBR and are difficult to realize in very large scale integration (VLSI) due to their lack of consideration for hardware implementation and modeling. Consequently, we present a hardware-oriented CBR-control algorithm that uses simple CBR control functions instead of requiring root and exponential operations to realize the real-time low-power design objective for HEVC applications within a mobile MPSoC. Then, an adequate hardware architecture with low hardware complexity is exploited to accomplish a low-power and high-speed VLSI design of a CBR controller for our proposed algorithm. Using diverse video-sized sequences under on-demand system coding-bit-rate constraints, the experimental outcomes demonstrate that the introduced design is capable of low power consumption and high speeds and can utilize low-complexity hardware.

Retaining the reconstruction quality of electrocardiogram (ECG) data compression is crucial for diagnosis demands. However, traditional wavelet-based approaches suffer from complicated distortion control. The most fundamental way to overcome this difficulty is to avoid the use of the time-domain distortion measure that requires the complete decoding process. In this article, based on the reversible roundoff nonrecursive discrete periodized wavelet transform reversible round-off non-recursive discrete periodized wavelet transform (RRO-NRDPWT), a new transform-domain index is presented. This index accumulates the roundoff error of the RRO-NRDPWT and the quantization error as the distortion measure. The index referred to as the simplified percentage root-mean-square difference (SPRD) can completely replace the PRD for the case of ${\mathbf{PRD}} \geq 2{\mathrm{\% }}$PRD≥2%, where $\boldsymbol{SPRD}/\boldsymbol{PRD} \approx 1$SPRD/PRD≈1. By using the ECG signals in the MIT-BIH arrhythmia database, the simulation results show that for target PRD (${\mathbf{PR}}{{\mathbf{D}}_{\mathbf T}}$PRDT) equals to $3{\mathrm{\% }} \pm 0.05$3%±0.05, the SPRD can save 99.34% quantization process time compared with the traditional quality control scheme.

In this paper, a speed and power-efficient set partitioning in hierarchical trees (SPIHT) design is introduced for one-dimensional (1-D) wavelet-based electrocardiography (ECG) compression systems with quality guarantee. To achieve real-time and low-power design objectives toward wearable quality-on-demand (QoD) ECG applications, we first propose a coding-time- and computation-efficient SPIHT algorithm using various types of coding status register files to overcome the disadvantages of low coding speeds and complicated hardware architectures characterizing prior SPIHT algorithms resulting from the necessity of dynamic computation and arrangement in the sorting and refinement processing phase. Second, a highly pipelined and power-efficient very large scale integration (VLSI) architecture is developed to implement a high-performance and low-power SPIHT design based on the proposed algorithm. The final simulation results demonstrate that our proposed algorithm can speed up the average coding time 1.52 to 2.74 times compared to prior work with an identical compression ratio for an 11-level $1024\times 1\,1-{\rm{D}}$ discrete wavelet transform at diverse target percentage root-mean-square differences (PRDT) on various MIT-BIH arrhythmia datasets. Applied to wearable wavelet-based QoD ECG applications, our proposed VLSI architecture attains a working frequency of 740 MHz and consumes an average of $\text{23}\ \mu {\text{W}}$ of power with Taiwan Semiconductor Manufacturing Company 90-nm CMOS technology, which shows the effectiveness of speed and power over the state-of-the-art designs.

In this paper, a machine learning (ML)-based power-efficient motion estimation (ME) controller algorithm and VLSI architecture incorporating coding bandwidth and rate-distortion (R-D) cost using convex optimization are proposed to effectuate a smart and bandwidth-efficient ME design for intelligent mobile systems. To be smart and adapt to time-altering coding bandwidth using intelligent power-management techniques in modern application processor systems, we first propose an ML-based bandwidth-on-demand ME controller algorithm based on the convex optimization method to resolve the lack of an awareness of coding bandwidth in prior ME designs. Then, a hardware-friendly and power-efficient VLSI architecture is developed to implement an intelligent, high-performance, and low-power ME controller design that can be combined with prior ME designs to satisfy the bandwidth-efficient ME design target under bandwidth constraints. The final implementation results show that the proposed smart ME controller architecture using our proposed bandwidth control scheme costs 0.816K gate counts, consumes 0.873 mW of power at a working frequency of 1.1 GHz with Taiwan Semiconductor Manufacture Company (TSMC) 90-nm CMOS technology, and achieves an average bandwidth reduction of 56.08% compared with previous non-bandwidth-on-demand ME designs for high-definition (HD) videos.

This paper proposes a data bandwidth-oriented motion estimation design for resource-limited mobile video applications using an integrated bandwidth rate distortion optimization framework. This framework predicts and allocates the appropriate data bandwidth for motion estimation under a limited bandwidth supply to fit a dynamically changing bandwidth supply. The simulation results show that our proposed algorithm can achieve 66% and 41% memory bandwidth savings while maintaining an equivalent rate-distortion performance and meeting real-time targets, when compared with conventional approaches for low-motion and high-motion D1 (704ntn 576)-size video, respectively. The final implementation costs 122 K gate counts with TSMC 0.13-μ m CMOS technology and consumes 74 mW of power for D1 resolution at 30 frames/s which is 40% of that achieved in previous designs.