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This brief presents a second-order discrete-time (DT) modified feed-forward (FF) delta-sigma modulator. To reduce the attenuation of the quantizer’s input signal due to switched-capacitor (SC) passive summing, the proposed modulator eliminates the internal FF path and reduces the number of input signals of the adder. A 4-bit asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporated with a passive adder is used to reduce power consumption and area. To allow the conversion delay of the SAR ADC, a delayed feedback is adopted. The prototype ADC is fabricated in a $0.11~\mu \text{m}$ CMOS process using four metal layers with an active die area of 0.165mm2. It achieves a dynamic range (DR) of 96.3 dB and a peak signal-to-noise and distortion ratio (SNDR) of 93.9 dB in a 2 kHz signal bandwidth while consuming $62.43~\mu \text{W}$ from a 1.8V/1.65V power supply, corresponding to a Schreier figure-of-merit (FOM) of 171dB.

This article proposes a low common-mode (CM) noise full-bridge LLC resonant converter with two balanced resonant tanks. In the proposed converter, each resonant inductor and capacitor is divided into two components with the same value. The CM current flowing through parasitic capacitors of the transformer is reduced due to the balanced resonant tank. Moreover, the CM noise can be significantly reduced by adjacently locating the primary and secondary layers with the same dv / dt characteristic. Therefore, the proposed converter decreases the CM noise generated from the planar transformer (PT) by the balanced resonant tank and proposed layer arrangement of PT and achieves a high power density with a decreased size of the electromagnetic interference filter. The validity of the proposed converter is verified by a 1.5-kW prototype with 400-V input and 270–420-V output.

A new structure of the transformer and its winding layout are proposed to reduce the common-mode (CM) noise generated from the planar transformer (PT). In the proposed converter, two half-bridge LLC resonant converters are connected in parallel on the primary side, and the secondary side of them is connected in series. The proposed converter can be utilized for the medium-to-high power applications due to the full-bridge structure of the primary side. For each transformer, one of the terminals is connected to the static point, which has zero dv / dt characteristic. Thus, the primary-side layer can have the same dv / dt characteristics with the secondary-side layer. By adjacently locating the primary and secondary layers, which have the same dv / dt characteristic, the CM current and noise generated from PT can be significantly reduced. Therefore, the proposed converter can achieve a high power density by reducing the size of the electromagnetic interference filter.