Search

In this letter, we report the influence of p-GaN body doping concentration on the ON-state performance of vertical GaN trench MOSFETs. Decreasing the p-GaN body doping concentration leads to an enhanced maximum drain current ( ${I} _{D,\max}$ ), reduced specific ON-resistance ( ${R} _{ \mathrm{\scriptscriptstyle ON},\mathrm{sp}}$ ), but also a decreased threshold voltage ( ${V} _{th}$ ), suggesting that the p-GaN doping plays an important role in balancing the ${V} _{th}$ , ${R} _{ \mathrm{\scriptscriptstyle ON},\mathrm{sp}}$ and ${I} _{D,\max}$ in vertical GaN trench MOSFETs. Resulting from the tuning of Mg concentration in the p-GaN, we demonstrate high ON-performance including a high ${I} _{D,\max}$ of 2.8 kA/cm2, a low ${R} _{ \mathrm{\scriptscriptstyle ON},\mathrm{sp}}$ of 0.87 $\text{m}\Omega \cdot $ cm2, a large ${V} _{th}$ of 4.8 V in a quasi-vertical GaN trench MOSFET on sapphire with a 2.5- $\mu \text{m}$ -thick drift layer, while maintaining a breakdown voltage of 273 V.

In this article, we demonstrate normally-OFF p-GaN gate high electron mobility transistors (HEMTs) on Si with an ultrahigh breakdown voltage ( ${V}_{BR}$ ) and excellent saturation drain current. Benefiting from the optimized material growth of high-resistivity buffer, effective Al2O3 surface passivation with suppressed OFF-state leakage current, and proper management of the electric field on the p-GaN gate edge, the device with a gate–drain distance of $18.5~\mu \text{m}$ exhibits a ${V}_{BR}$ of 1344 V at ${I}_{D}$ of $1~\mu \text{A}$ /mm with grounded substrates, the highest among all the reported normally-OFF GaN-on-Si transistors. Well-restored high-density 2-D electron gas and efficient gate modulation enable the device with a high ${I}_{DS,max}$ of 450 mA/mm and a low specific ON-resistance of 3.92 $\text{m}\Omega \cdot $ cm2. Moreover, a large threshold voltage of 1.6 V (at ${I}_{D}$ of $10~\mu \text{A}$ /mm) and a steep subthreshold slope of 66 mV/dec have been achieved, with negligible threshold voltage shift upon long-term forward gate stress at 150 °C. These results illustrate the great potential of p-GaN gate HEMTs on Si for beyond 600-V applications.

This letter reports on the suppression of reverse leakage current ( ${I} _{r}$ ) in $\beta $ -Ga2O3 Schottky barrier diodes (SBDs) through Schottky barrier modification by a low power CF4-plasma treatment prior to Schottky metal deposition. Revealed by an x-ray photoelectron spectroscopy (XPS) analysis, the fluorine-plasma treatment brought an incorporation of fluorine ions and depletion of silicon donors in the near surface region of the $\beta $ -Ga2O3, and thus raised its surface potential by around 0.14 eV. Furthermore, insulating GaF x was likely created at the Schottky interface. Attributed to the fluorine-plasma- modified Schottky barrier, a reduced ${I} _{\mathbf {r}}$ by around four orders of magnitude and enhanced blocking voltage ( ${V} _{{block}}$ ) from 150 V to 470 V at ${I} _{r} = 100\mu $ A/cm2 have been achieved without degrading the forward characteristics. Different from the untreated device whose ${I} _{r}$ was purely governed by the thermionic field emission (TFE), the fluorine-plasma-treated SBD showed a greatly suppressed TFE-current until a space-charge limited current (SCLC) started to dominate at around −500 V.

High performance NiO/ $\beta $ -Ga2O3 heterojunction pn diodes were realized by applying a sputtered p-type NiO film onto a lightly doped n-type $\beta $ -Ga2O3 epitaxial layer. Taking advantage of the high barrier height against carriers within the pn heterojunction, the demonstrated device exhibited a high breakdown voltage ( ${V}_{B}{)}$ of 1059 V without optimized electric field management techniques, and before breakdown the reverse leakage current density remained below $1~\mu \text{A}$ /cm2. Simultaneously, a relatively low specific on-resistance ( $R_{\text {on, sp}}{)}$ of 3.5 $\text{m}\Omega \cdot \text {cm}^{{2}}$ was achieved. The built-in potential of the heterojunction that determined by a capacitance-voltage ( ${C}$ - ${V}$ ) measurement was around 2.4 eV. As discussed in terms of the energy band diagram of a type-II heterojunction, the conduction band and valence band offsets at the NiO/ $\beta $ -Ga2O3 hetero-interface were estimated to be 1.2 and 2.3 eV, respectively.

Dynamic characteristics of GaN HEMT grown on a native substrate were systematically investigated at 300K and 150K. Transfer and output characteristics of the GaN HEMT were measured after various off-state stressing conditions and recovery durations. In addition, a high-speed scheme was employed to finish the measurement within $75~\mu \text{s}$ , and to ensure maximum preservation of stressing/recovery consequences. The threshold voltage instability and current collapse commonly observed at room temperature were mostly diminished at 150K, which was attributed to reduced number of electrons through the metal-semiconductor contact and insufficient number of carriers overcoming the capture potential barrier. Two pulsed I-V measurements, including evaluations with various off-state quiescent bias points and “on-the-fly” on-resistance sampling, confirmed an inefficient electron capture process at 150K, with a time constant larger than dozens of seconds. The output characteristic comparison between hard switch and soft switch at 150K provided direct experimental evidence for electron capture promotion by hot carriers.

GaN offers an excellent potential for fabricating X-ray detectors, taking advantage of its superior material properties and well-developed manufacturing technologies. In this letter, we demonstrated a self-powered fast-response X-ray detection using GaN-based vertical p-n diodes grown on a bulk GaN substrate. Attributed to the high crystalline quality achieved by homoepitaxy, the fabricated photodiodes exhibited an excellent rectification behavior, and therefore, a strong photovoltaic response to X-ray illumination when biased at 0 V. The transient X-ray detection analysis revealed that the self-powered detectors have a relatively short response time ( $\cdot $ Gy $^{ {-{1}}}\cdot $ cm−2.

In this letter, we report high-performance p-GaN HEMTs on Si with robust gate operation. For the first time, the preserved OFF-state drain blocking capability has been demonstrated in p-GaN HEMTs after forward gate breakdown. Benefitting from the reduced metal/p-GaN contact region, the gate breakdown was limited to take place only at the metal/p-GaN junction, with the p-GaN/AlGaN/GaN junction intact. The device shows state-of-the-art characteristics with a large threshold voltage of 1.75 V at ${I}_{\text {D}}$ of $100~\mu \text{A}$ /mm (2.3 V by linear extrapolation), a high maximum drain current of 610 mA/mm at ${V}_{\text {GS}}$ of 8 V, a low specific ON-resistance of 1.8 $\text{m}\Omega \cdot \text {cm}^{{2}}$ , and a high breakdown voltage of 1100 V defined at ${I} _{\text {D}}$ of $1~\mu \text{A}$ /mm with grounded substrate.

We report on the power performance of GaN-on-Si metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs) with a high- ${k}$ ZrO2 gate dielectric formed by atomic layer deposition. As a result of the high-quality ZrO2 and ZrO2/AlGaN interface, the MOSHEMTs demonstrate an excellent ON/OFF current ratio of $5 \times 10^{10}$ , a steep subthreshold slope of 66 mV/dec, a small hysteresis of ~0.05 V, and a high breakdown voltage of 1084 V at $1~\mu \text{A}$ /mm. Effective suppression of current collapse with a dynamic-to-static ON-resistance ratio of 1.78 at a drain bias of 600 V is also achieved in the device. Benefiting from the highly uniform gate stack, large-area devices with a gate width of 20 mm were also demonstrated using the ZrO2 gate dielectric, exhibiting a maximum output current of 7.4 A, a low ON-resistance of $0.66~\Omega $ , and a high breakdown voltage of 650 V at an OFF-state drain current of $1~\mu \text{A}$ /mm.

Enhancement-mode GaN MOS-HEMTs with a uniform threshold voltage ( ${V}_{\text {th}}\sim \text {2.2 }\pm \text {0.25}$ V at ${I}_{D}= \text {1}\,\,\mu \text{A}$ /mm) have been achieved by a recess-free barrier engineering technique in conjunction with a high- ${k}$ gate dielectric. The design includes an ultrathin (~6 nm) Al0.2Ga0.8N barrier preserving the two dimensional electron gas (2DEG) mobility underneath the gate and a selective area barrier regrowth to restore the 2DEG at the access regions. A high- ${k}$ ZrO2 gate dielectric was employed to enhance the gate control over the channel. The common issue of recess-induced damage was mitigated. The high-quality gate stack results not only in a highly uniform and large ${V}_{\text {th}}$ , but also small hysteresis, minimal gate lag, low on-resistance, and high output current in the E-MOS-HEMTs.

An auto-zero-voltage-switching (ZVS) quasi-resonant LED driver with gallium nitride (GaN) FETs for general lighting applications is presented. The proposed LED driver switches at high frequency to minimize the inductors to microhenry range. ZVS can be automatically achieved with the proposed controller to eliminate switching loss. The GaN FETs enable high-frequency operation and improve the power efficiency. A fully integrated LED shunt protector is proposed to bypass the failed LEDs in series-connected LED strings. The overall lifetime of the LED strings can be improved, and the maintenance cost can be reduced. The characteristics of the ZVS quasi-resonant LED driver with small inductors and the conditions for ZVS are also discussed in detail. The LED driver is fabricated with a 0.35- $\mu \text{m}$ 120-V high-voltage process. It can provide up to 25-W power to the LED with $2 \times 3.3\,\,\mu \text{H}$ inductors and achieves 91.4% peak efficiency and a 0.973 peak power factor from 60-Hz 100- to 120- $\text{V}_{\mathrm {ac}}$ input.

This letter reports the monolithic integration of GaN-based driving vertical metal–oxide–semiconductor field-effect transistor (VMOSFET) on light-emitting diode (LED) with high output current density and bright-ness. By selectively regrowing a simple p- and n-GaN bilayer on top of an LED wafer, the VMOSFET was realized with an n/p/n structure and intrinsically connected with the LED through the bottom conductive n-GaN layer. During the fabrication, a tetramethylammonium hydride wet etch technique was employed to smoothen the sidewall channel surface of the VMOSFET and to enhance its channel electron mobility, consequently achieving a high output current density exceeding 1.4 kA/cm2. The integrated VMOSFET-LED exhibited a high light output power of 8.5 mW or 9.4 W/cm2 with a modulated injection current of 10 mA through the VMOSFET, showing a great potential of such integration scheme for a variety of smart-lighting applications.

Interface trapping is one of the most notorious effects that limit device performance in GaN-based MIS high electron mobility transistors (MISHEMTs). In this paper, we present a comprehensive study on interface traps in AlGaN/GaN MISHEMTs using low pressure chemical vapor deposition SiNx as gate dielectric. We combined the trapping analysis in MIS diodes and actual MISHEMTs to estimate the interface trap state densities ( $\text{D}_{\mathrm {it}})$ and their distributions in the device, and to investigate their influence on device electrical properties. Two types of interface traps with different emission time constants, designated as “slow” and “fast” traps, were identified and characterized by means of pulse-mode current-voltage measurements and a frequency dependent conductance method. It was found that “fast” traps located in the device access region could be effectively restrained by passivation using plasma enhanced chemical vapor deposition SiNx. However, “slow” traps, no matter whether located beneath the metal gate or in the access region, were less influenced by passivation. Due to the strong interference of traps in the access region, $\text{D}_{\mathrm {it}}$ extraction using the conventional conductance method was not accurate for the lateral GaN-based MIS diodes. A modified small-signal equivalent circuit that includes the impedance of traps in the access region is proposed. Proper passivation for the device access region is essential when using the conductance method for GaN-based MIS devices.

In this paper, we present a systematic investigation of metal–organic chemical vapor deposition-grown in situ SiN as the gate dielectric and surface passivation for AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs). The dielectric constant and breakdown field of the in situ SiN were extracted from devices with varied gate dielectric thicknesses. Using frequency-dependent capacitance–voltage and parallel conductance methods, we obtained a low trap density of $\sim 3\times 10^{12}$ cm $^{-2}$ eV $^{-1}$ at the SiN/AlGaN interface. The MISHEMTs with a source–drain distance of $3~\mu \text{m}$ show a maximum drain current of 1560 mA/mm and a high on/off current ratio of $10^{9}$ . The device threshold voltage ( ${V}_\textsf {th}$ ) stability was assessed by means of both negative and positive gate stress measurements, as well as temperature-dependent $ {I}_\textsf {D}$ – ${V}_\textsf{G}$ measurements. We observed a minimal $ {V}_\textsf{th}$ shift of ~0.4 V under both 3000 s gate stress of ${V}_\textsf {GS}= 4$ V and up to 200 °C thermal stimulation. Furthermore, combining the in situ SiN with plasma-enhanced chemical vapor deposition SiN, we developed a bilayer passivation scheme for effective suppression of current collapse. Employing the high-quality in situ SiN, we have demonstrated large-area GaN MISHEMTs on Si with a gate width of 20 mm, showing a low off-state leakage of $2~\mu \text{A}$ /mm at 600 V and a low dynamic/static ON-resistance ratio. The device results show great advantages of employing in situ SiN in D-mode GaN MISHEMTs for high-efficiency power switching applications.

In this letter, a novel monolithically integrated Si-GaN cascoded FET is designed and experimentally demonstrated for high-voltage power switching applications. The device is formed by monolithically connecting a low-voltage Si MOSFET and a high-voltage normally-on GaN MIS-HEMT on the same substrate in the cascode configuration. The interconnection distance is $50~\mu \text{m}$ which is only 2.5% of that of the conventional two-chip co-package approach (~2 mm). The fabricated cascoded FET features normally-off functionalities with a threshold voltage of 3.2 V, a drive current of 1850 A/cm2 (630 mA/mm) at the gate bias of 15 V, a gate swing of 20 V, a specific on-resistance of $3.3\;\text {m}\Omega \cdot \text {cm}^{2}$ and a breakdown voltage of 696 V.

This paper reports on the fabrication and characterization of gate-last self-aligned in situ SiN x /AlN/GaN MISHEMTs. The devices featured in situ grown SiN x by metal–organic chemical vapor deposition as a gate dielectric and for surface passivation. Selective source/drain regrowth was incorporated to reduce contact resistance. SiN x sidewall spacers and low- $\kappa $ benzocyclobutene polymer ( $\kappa =2.65$ ) supporting layers were employed under the gate head to minimize the parasitic capacitance for high-frequency operation. The device with a gate length ( $L_{G})$ of $0.23~\mu \text{m}$ exhibited a maximum drain current density ( $I_{\rm DS})$ exceeding 1600 mA/mm with a high ON/OFF ratio ( $I_{\mathrm{{\scriptscriptstyle ON}}}/I_{\mathrm{{\scriptscriptstyle OFF}}})$ of over $10^{7}$ . The current gain cutoff frequency ( $f_{T})$ and maximum oscillation frequency ( $f_{\max })$ were 55 and 86 GHz, respectively. In addition, the effect of temperature, from room temperature up to 550 K, on the dc and RF performances of the gate-last self-aligned MISHEMTs was studied.