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The high peak mobility of 509 cm2/ $\text {V}\cdot \text {s}$ of the chemical vapor deposition -grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and surface roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.

The electron mobility in junctionless (JL) Ge nanowire nFETs with the $\langle 110\rangle $ channel direction is calculated and compared with experimental data. The calculation of the electron mobility is based on the Kubo–Greenwood formula. The wave functions are obtained by solving the self-consistent Poisson–Schrodinger equation. Phonon scattering, surface roughness scattering, and Coulomb scattering (CS) by interface charges and channel charges are considered. Carrier screening on Coulomb charges is calculated using Lindhard’s screening theory. At low electron densities, the JL channels have lower electron mobility than inversion-mode (IM) channels due to CS from channel charges. At high electron densities, CS in JL channels is effectively reduced by screening, resulting in mobility comparable with the IM channels. The L4 electrons have higher mobility than $\text{L}4^\prime $ electrons. Applying uniaxial tensile strain along the channel can lower the energy of L4 valleys to enhance the channel mobility.

The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress ( $\vert \sigma _{r}\vert )$ does not equal to that of tangential stress ( $\vert \sigma _{\theta }\vert )$ on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.