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The related recovery mymargin mymargin effect of hydrogen on AlGaN/gallium nitride (GaN) high-electron-mobility transistors (HEMTs) irradiated by high-fluence protons was investigated in this article. The results show that under the same temperature and time conditions, the recovery effect induced by thermal hydrogen annealing is better than that of ordinary thermal annealing. Compared with the ordinary thermal annealing, the high-fluence proton-irradiated device experienced a 65-mA additional increase in saturation current at the gate-to-source voltage ( $V_{\mathrm {gs}}$ ) of 0 V, a 0.074-V additional negative shift of the threshold voltage, a more significant increase in reverse gate leakage current and better gate lag after the hydrogen treatment. The defect densities are extracted by the low-frequency noise method. It shows that the trap density decreases from $8.32\times 10^{17}$ to $6.84\times 10^{\mathrm {17 {}}}$ cm $^{-3}\cdot $ eV $^{-1}$ after ordinary thermal annealing and then decreases from $6.84\times 10^{17}$ to $3.85\times 10^{17}$ cm $^{-3}\cdot $ eV $^{-1}$ after hydrogen treatment of an irradiated AlGaN/GaN HEMT. The mechanism for the decrease of trap density after the hydrogen treatment could be attributed to the H-passivated defects in the structures of AlGaN/GaN HEMTs.

The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened wafers with silicon ion implantation and unhardened wafers are investigated. A TID-hardened PDSOI MOSFET up to 1 Mrad(Si) is obtained by Si+ implantation in buried oxide (BOX). The hardening benefits from the electron traps in the BOX introduced by Si+ implantation. Although the radiation hardening process has a rare impact on nominal electrical characteristics of the device before irradiation, it will affect the NBTI reliability, which is manifested as the decrease in the NBTI lifetime for the radiation-hardened devices. The energy distribution of positive charges built up during NBTI stress is obtained. It proves that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during the NBTI stress. This conclusion is also verified by the low-frequency noise characteristics.

Neutron-induced secondary ions and their contribution to a single-event upset (SEU) in SRAM are investigated by Geant4 and TCAD simulations. It proves that the maximum linear energy transfer (LET) values of secondary ions produced by neutron–nuclear reactions can be as high as 31.5MeV-cm2/mg, while the LET value of 99.8% secondary ion is 2 MeV-cm2/mg could induce an SEU in this 65-nm SRAM. Then, these results are used to calculate the atmospheric neutron-induced soft-error rate (SER). The calculated SER is verified by field testing and 14-MeV neutron-accelerated testing.

Real-time soft error rate of 65-nm QDRII+ static random access memory was measured on the Tibetan-plateau with an altitude of 4300 m. Error types including single-bit upset (SBU), multiple-cell upset (MCU), and burst errors were observed. The MCU ratio is 23%, with a maximum size of nine cells. Majority of the MCU events are vertically oriented along the well stripes. Monte Carlo simulations were further performed to study the characteristics of the neutron-induced secondary ions. Diverse secondary ion species, from the proton to Re, were found, which were significantly affected by the presence or absence of the tungsten layer. The impact of neutron energy on the linear energy transfer (LET), range, and deposited charge of secondary ions in the sensitive volume was revealed.

Single-event upset sensitivity of 55- and 180-nm SRAM devices with error detection and correction (EDAC) exhibits obvious ion flux and scrubbing time dependence. On-orbit soft error rates (SERs) of EDAC SRAM devices are extrapolated from accelerator heavy-ion data and compared with rectangular parallelepiped-predicted SER, based on an experimentally verified formula. It is found that on-orbit SER of EDAC SRAM is contributed by both the memory array and the EDAC circuitry. This method can guide the optimization of EDAC SRAM hardening strategy and also the on-orbit hardness assurance.