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This paper discusses design methodologies for high-speed SAR ADCs. A comparison of various architectures and the study of benefits and limits identify the best solution for high-speed and medium resolution. It is an interleaving architecture with the channel implemented by a fast coarse SAR quantizer and 2-way time-interleaved (TI) fine SAR ADCs. We propose a float-then-write code transfer technique for optimizing the transfer sequence and reducing the reference interference. Furthermore, we also study and compare the output impedance of the reference generation as well as the reference interference for the optimized code transfer scheme and the conventional bit-by-bit in both single-channel and TI scenarios. In addition, the mismatches in TI channels and two sub-ADCs are discussed. A 10-bit test vehicle fabricated in 65-nm CMOS confirms experimentally the proposed methods operating with 1.2-V supply at 700 MS/s. The circuit occupies an active area of 0.084 mm2 and achieves a signal-to-noise and distortion ratio at a Nyquist of 53.3 dB, with a power consumption of 9.5 mW. The Walden figure-of-merit is 36 fJ/conversion-step.

This brief presents a 7-bit 700-MS/s four-way time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A partial $V_{\mathrm {cm}}$ -based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. Compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. In addition, the impacts of such a reduction on the comparator offset, noise, and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in a 65-nm CMOS technology occupies an active area of 0.025 mm2. The measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio of 40 dB at Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden FoM of 48 fJ/conversion step.